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IEE Proceedings G (Circuits, Devices and Systems)

Volume 139, Issue 3, June 1992

Volumes & issues:

Volume 139, Issue 3

June 1992

Analysis of a Class E rectifier with a series capacitor
  • Author(s): M.K. Kazimierczuk  and  W. Szaraniec
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 269 –276
  • DOI:  10.1049/ip-g-2.1992.0046
  • Type: Article
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  • p. 269 –276 (8)
    The analysis, design procedure, and experimental results are presented for a Class E rectifier. The circuit consists of a diode, a series capacitor, and a second-order lowpass filter. The diode ON duty cycle and the ripple voltage are decoupled, i.e. the two parameters are determined by different circuit elements. The diode turns on at low |dv/dt| and turns off at zero dv/dt and low |di/dt|, reducing both switching losses and noise. The circuit has a step-down AC–DC voltage transfer function and therefore is especially suitable for applications in low-output-voltage power supplies. The experimental and calculated results were in good agreement.
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Computer-aided interactive filter design using templates
  • Author(s): M.R. Frater  and  D.B. Pike
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 277 –286
  • DOI:  10.1049/ip-g-2.1992.0047
  • Type: Article
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  • p. 277 –286 (10)
    Particular properties of symmetric lattices provide a convenient basis for the development of an empirical approach, based on templates, to the design of analog filters. These templates can be used for the design of filters with demanding specifications for attenuation and phase responses, and also for the design of equalisers. This paper presents an effective interactive computer tool as part of a computer-aided approach to this problem, and presents significant extensions to the theory to enable the designer to determine the transfer function by specifying the desired attenuation at a number of points. The design leads to reactance functions that define the arms of a symmetric lattice. The transfer function of the filter is also produced, and can be used to give other realisations.
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Radiation hardened high performance CMOS VLSI circuit designs
  • Author(s): H. Hatano
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 287 –294
  • DOI:  10.1049/ip-g-2.1992.0048
  • Type: Article
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  • p. 287 –294 (8)
    For space or nuclear plant applications, radiation tolerant high performance CMOS VLSI circuit designs, utilising scaled CMOS/SOS technology and scaled bulk CMOS technology, have been reviewed, placing strong emphasis on total dose radiation hardness. Based on radiation induced degradations for conventional CMOS circuits, such as inverters, ring oscillators and memory circuits, total dose radiation hardening technologies have been discussed. Low temperature process and thin oxide introductions are effective for radiation induced threshold voltage shift reduction. Total dose radiation induced field leakage is suppressed by introducing a thin field oxide between the source/drain diffusion layers and a thick field oxide in NMOS transistors, combined with the buried P+ diffusion layer at the P well edge, without sacrificing speed performance. In addition to device/process technologies for total dose radiation hardening, usefulness for NAND logics and static circuits in radiation tolerant CMOS VLSI designs, are shown. Furthermore, radiation tolerance superiority of clocked gate CMOS circuits to transfer gate CMOS circuits in SOS devices, are indicated. Latchup immunity and SEU immunity have also been discussed, for both SOS and bulk devices. Effectiveness of epitaxial substrate and wide transistor introductions for latchup and SEU prevention, is shown, respectively. CMOS/SOS radiation hardened VLSIs and bulk CMOS radiation hardened VLSIs which have been developed by utilising above mentioned technologies, are reported. The entire work described in this paper has made it possible to design radiation hardened high performance VLSI circuits for space or nuclear plant applications, utilising both CMOS/SOS technology and bulk CMOS technology.
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Optimisation approach to the analysis of piecewise-linear convex circuits
  • Author(s): S. Osowski
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 295 –300
  • DOI:  10.1049/ip-g-2.1992.0049
  • Type: Article
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  • p. 295 –300 (6)
    The paper presents an optimisation approach to the investigation of piecewise linear convex circuits. The problem is formulated in terms of the objective function and linear equality constraints applied to the diode circuits. Two efficient techniques for solving such a problem are presented. One is based on the active constraints strategy and implemented in the form of a numerical program, and the second one is based on the neural principle and implemented in analogue circuitry, solving the problem in real time. Results of numerical experiments illustrate the theoretical considerations.
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Conjugate gradient algorithm for efficient training of artificial neural networks
Fault diagnosis in large analogue circuits based on hybrid decomposition
  • Author(s): A.A. Hatzopoulos  and  J.M. Kontoleon
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 311 –318
  • DOI:  10.1049/ip-g-2.1992.0051
  • Type: Article
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  • p. 311 –318 (8)
    Fault location in analogue circuits is treated using a hybrid decomposition technique. The method is based on linear fault diagnosis (FD) equations and node-voltage measurements under the desired current excitations. The circuit is divided into subcircuits using a combination of node and branch decomposition techniques. The consistency of the FD equations using nominal element values and the measured node voltages is checked to locate the faulty subcircuits. Built-in self-test in analogue circuits may also be implemented based on the proposed method and following the given practical tolerance considerations, which overcome the need for a pretest circuit analysis. Demonstrative examples are given to show the effectiveness of the proposed technique.
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Performance prediction and function recovery of CMOS circuits damaged by Co-60 irradiation
Five-parameter DC GaAs MESFET model for nonlinear circuit design
  • Author(s): J. Rodriguez-Tellez  and  P.J. England
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 325 –332
  • DOI:  10.1049/ip-g-2.1992.0053
  • Type: Article
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  • p. 325 –332 (8)
    An improved gallium arsenide (GaAs) MESFET model for nonlinear large-signal circuit design is described, together with the parameter estimation and optimisation techniques. The new model is based on the work of Curtice and offers significant advantages in the simulation of the device in the low-current region. This is achieved by modelling the bias dependency of the pinch-off voltage. Data showing the bias dependency of the device model parameters is provided and a comparison between the new model, the Curtice model and the Schichman-Hodges FET model is made, with the use of a wide variety of different size devices. The software modules for the automated characterisation and modelling of GaAs devices are also described.
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Microwave probe for circuit/device testing
  • Author(s): J. Rodriguez-Tellez
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 333 –338
  • DOI:  10.1049/ip-g-2.1992.0054
  • Type: Article
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  • p. 333 –338 (6)
    A probe for the high frequency measurement of discrete semiconductor devices in a naked form is described. Because conventional coplanar based probes cannot measure such devices directly, an artificial package usually needs to be fabricated to enable the device to be probed via the artificial package pads. The new probe avoids this need and overcomes the severe problems normally encountered in de-embedding the packaging effects from the device data. The design of the probe and its RF performance is described with the use of GaAs terminations. The usefulness of the probe in assessing packaging effects in microwave bipolar devices is demonstrated by measuring the S-parameters of a bipolar device in a naked and packaged environment.
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Software based linearisation of thermistor type nonlinearity
Optically driven photoconductive devices for power switching application. Part 1: theory and experimental results
  • Author(s): H. Shakouri  and  J.J. Liou
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 343 –349
  • DOI:  10.1049/ip-g-2.1992.0056
  • Type: Article
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  • p. 343 –349 (7)
    The photoconductive circuit element (PCE) can be made relatively compact, can hold off a large voltage when the light is off and can conduct a large current when the light is on. Thus the PCE is an attractive device for power switching applications. The authors have designed, fabricated and measured several prototype (scaleddown) PCEs to study the feasibility of using such devices for power-switching purposes. Physical insights and theoretical analysis are also discussed. Qualitative agreements are found between experimental data and the results calculated from a recently developed numerical model.
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Optically driven photoconductive devices for power switching application. Part 2: Thermal modelling including heat sink
  • Author(s): J.J. Liou  and  J.S. Yuan
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 350 –355
  • DOI:  10.1049/ip-g-2.1992.0057
  • Type: Article
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  • p. 350 –355 (6)
    The removal of heat generated in power devices using a heat sink is increasingly important for packaging and reliability, particularly for the photoconductive circuit element (PCE) which can conduct a large current when used as a high power switch. The paper presents a thermal model for estimating the relationship between the temperature in a p+-i-n+ PCE and the required geometry of the heat sink under steady-state dark and illuminated operations. The model is based on a one-dimensional heat-transfer analysis and relevant semiconductor device physics. Given the bias condition, the geometry and the material for the PCE, and the material for the heat sink, the model can predict the area of the heat sink needed for a desired temperature in the device. Calculations for different semiconductor thicknesses, different metals (aluminum and copper), different semiconductors (Si and GaAs), different applied voltages, different levels of optical excitation and different device operations (turn-on and turn-off operations) are illustrated.
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Sigma-delta modulators with multibit quantising elements and single-bit feedback
  • Author(s): T.C. Leslie  and  B. Singh
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 356 –362
  • DOI:  10.1049/ip-g-2.1992.0058
  • Type: Article
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  • p. 356 –362 (7)
    The performance of multibit sigma-delta coders is analysed and compared with that available from single-bit designs. It is demonstrated that the basic difficulty with multibit coders is the need for a high-accuracy digital-analogue convertor (DAC) in the feedback loop. An expression for the reduction of in-band noise power as a function of coder order, quantiser resolution, and oversampling ratio is derived, together with a subsidiary condition imposed by the use of multibit DACs. New coder topologies are presented which use multibit quantisation with single-bit feedback, avoiding the need for high-resolution DACs. Analysis and simulations are described which show that these have a similar performance to multibit designs with multibit feedback.
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Designing filters for polyphase filter banks
  • Author(s): J.-H. Lee  and  W.-J. Kang
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 363 –369
  • DOI:  10.1049/ip-g-2.1992.0059
  • Type: Article
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  • p. 363 –369 (7)
    The paper concerns the filter design problem for a recently-proposed polyphase filter bank with an arbitrary number of subband channels. We develop an analytical formula for the design of a prototype filter used in the polyphase filter bank. Compared with direct numerical design methods, this formula-based method allows the design of the required FIR lowpass prototype filter with a much lower complexity of operation and better filter bank performance. We further extend the theoretical results to two dimensions. Examples are also presented.
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Design, selection and implementation of flash erase EEPROM memory cells
  • Author(s): A.A.M. Amin
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 370 –376
  • DOI:  10.1049/ip-g-2.1992.0060
  • Type: Article
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  • p. 370 –376 (7)
    The paper reports an investigation into the design and process constraints of FLASH EEPROM memory cells. It describes several possible structures which were developed by the MOS memory R&D group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of 5 major structures are described. The paper discusses the principle of operation, advantages and disadvantages of each of these structures. It also includes characteristic results and discussion of the performance of these candidate cells.
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Noise characteristics of n-channel deep-depletion mode MOS transistors
  • Author(s): C. Carruthers  and  J. Mavor
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 377 –383
  • DOI:  10.1049/ip-g-2.1992.0061
  • Type: Article
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  • p. 377 –383 (7)
    The potential of deep-depletion MOS transistors for a low-noise, analogue signal-processing application is investigated in this paper. These are predicted to have a favourable noise performance, because a buried depletion layer in this transistor structure can be induced between its conduction channel and the SiO2–Si interface noise mechanisms, which dominate a surface-channel device. Measurements for n-channel depletion-mode MOS transistors formed on p-type <100> orientation silicon substrates are presented. Under certain bias conditions these devices exhibit a significant reduction in the low-frequency noise performance over conventional, surface-channel MOS structures. A BiCMOS cascode buffer circuit is proposed, which yields a favourable noise performance for infra-red, focal-plane signal-processing applications.
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Systolic array architecture implementation of parasitic-insensitive switched-capacitor filters
  • Author(s): R. Raut ; B.B. Bhattacharyya ; S.M. Faruque
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 384 –394
  • DOI:  10.1049/ip-g-2.1992.0062
  • Type: Article
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  • p. 384 –394 (11)
    A systematic procedure is developed for implementing switched-capacitor filters in systolic array architecture. The most complete signal flow graphs that satisfy the conditions of a systolic array, and also the general first-and second-order transfer functions, are considered. A step-by-step reduction procedure is then developed for the second-order signal flow graphs that yield structures which can be implemented with a minimal amount of hardware in LSI/VLSI technology. Implementation of switched-capacitor filters using these reduced signal flow graphs is discussed. Some structures that are not strictly systolic are also considered for second-order filters. Generation of parasitic-insensitive second-order switched-capacitor filters using systolic array architecture are, however, treated in detail, both for biphase (two-phase) and for four-phase clocking schemes. Guidelines for minimising the total capacitance are given and the sensitivity characteristics are provided. Systolic array architecture realisation of a higher-order switched-capacitor filter is illustrated. Results obtained from a bandpass switched-capacitor filter, implemented on a VLSI workstation (SUN) supporting a 3 μm CMOS technology, are reported. Simulation results for a fourth-order filter realised using systolic array architecture are provided.
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Inversion of continued-fraction expansion of multidimensional transfer functions using derivatives and graphs
The effect of substrate resistivity on threshold voltage shifts due to radiation-induced damage in IGFET
  • Author(s): A.D. Savio ; P.K. Bhattacharya ; G.S. Kousik ; R.P. Nandakumar
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 400 –404
  • DOI:  10.1049/ip-g-2.1992.0064
  • Type: Article
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  • p. 400 –404 (5)
    This paper describes the dependence of the radiation-induced threshold voltage shift (δVt) of n-channel IGFET devices on the substrate doping concentration and the concentration of segregated boron atoms in the oxide. Substrate resistivities of 0.1 and 0.5 Ω/cm were used. The thicknesses of the investigated gate oxides varied from 17.0 to 50.0 nm. The devices were irradiated with Al Kα (1.49 keV) X-rays to different radiation doses at identical dose rates. The threshold voltages were measured before and after irradiation, employing an optically assisted hot electron injection technique. Following irradiation and hot electron injection, the threshold voltage shifts due to fixed positive charge (ΔVFPC) and neutral electron traps (ΔVNET) were determined. The radiation-induced threshold voltage shifts due to FPCs were greater for the 0.5 Ω/cm wafer than for the 0.1 Ω/cm wafer, and the threshold voltage shifts due to NETs were greater for the 0.1 Ω/cm substrate. The interface concentration of boron in the oxide at different depths obtained from Suprem-III simulations was related to induced threshold voltage shifts.
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Simple analytical model for short-channel MOS devices
  • Author(s): H.-C. Chow ; W.-S. Feng ; J.B. Kuo
  • Source: IEE Proceedings G (Circuits, Devices and Systems), Volume 139, Issue 3, p. 405 –409
  • DOI:  10.1049/ip-g-2.1992.0065
  • Type: Article
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  • p. 405 –409 (5)
    A simple analytical model derived from a quasi-two-dimensional analysis with a nonvanishing E-field derivative at the pinchoff point and a continuous output conductance at the transition point for short-channel MOSFETs is presented. This model also covers mobility reduction, carrier velocity saturation, body, channel-length modulation, source-drain series resistance and short-channel effects for an accurate determination of the pinchoff point location without internal numerical iterations as compared to other models. This model can be used to describe the channel-length modulation effects more accurately in circuit simulation with short-channel MOSFETs.
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Simple and direct computer simulation of continuous-mode resonant convertors in steady state

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