IEE Proceedings G (Electronic Circuits and Systems)
Online ISSN
2053-7964
Print ISSN 0143-7089
Print ISSN 0143-7089
Published from 1980-1988, IEE Proceedings G contained significant and original contributions on electronic circuits and systems.
This journal was previously known as Proceedings of the Institution of Electrical Engineers 1963-1979. ISSN 0020-3270. more..
This journal was previously known as IEE Journal on Electronic Circuits and Systems 1976-1979. ISSN 0308-6984. more..
This publication is continued by IEE Proceedings G (Circuits, Devices and Systems) 1989-1993. ISSN 0956-3768. more..
Volumes & issues:
Latest content
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Low power dynamic ternary logic
- Author(s): J.-S. Wang ; C.-Y. Wu ; M.-K. Tasi
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p.
221
–230
(10)
A new dynamic ternary logic and its circuit structures have been developed to achieve the goal of low power dissipation and high operation speed. Based on the selected ternary algebra, a dynamic ternary logic system can be implemented by simple ternary gates (STGs), with positive or negative ternary inverters connected to all the input terminals. An overlapped four-phase clocking scheme is needed, and the connection of different circuit blocks has to follow the permitted fan-out diagrams. As compared to the static ternary logic, the dynamic ternary logic has a lower DC power dissipation and an operation speed approximately twice as fast. Typical powerdelay product of a simple ternary inverter in 2 µm CMOS is 3 fJ. Moreover, as compared with binary circuits, the ternary circuit has better performances of the power-delay product and less terminal leads per functional circuit. These features make the dynamic logic circuits quite attractive in VLSI/ULSI applications.
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8 × 8 bit pipelined dadda multiplier in CMOS
- Author(s): D.G. Crawley and G.A.J. Amaratunga
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p.
231
–240
(10)
Parallel multiplication schemes for VLSI have traditionally been chosen for their regular layout. Unfortunately, this has meant using algorithms which are not time-optimal. In the paper, we present an 8 × 8 bit time-optimal multiplier using the Dadda scheme implemented as a 7-stage linear pipeline. The design uses automated layout techniques to avoid the problems associated with the irregularity of the scheme, and a 3 μm n-well CMOS process with two layers of metal. The use of multiple levels of metal reduces the delay associated with the interconnection between cells and also permits the over-routing of active circuitry. A new pipelined carry look-ahead adder is used for the final summation, and this provides a significant contribution to the performance of the multiplier. A set of cells was designed for the multiplier and some aspects of their design are discussed. In particular, a previously unreported Vdd overshoot problem in an existing exclusive-OR gate circuit is described and explained. The multiplier is expected to operate at a maximum clock frequency of at least 50 MHz.
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Piecewise polynomial models for MOSFET DC characteristics with continuous first order derivative
- Author(s): Y.-H. Jun and S.-B. Park
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p.
241
–246
(6)
The measured DC characteristics of MOSFET show monotonically increasing smooth curves for given gate-to-source voltage. The paper describes two methods of polynomial approximation to these curves with continuous first order derivative of drain current with respect to drainto-source voltage, which is often required for convergence in the circuit simulation. The polynomial coefficients, as a function of gate-to-source voltage, are so determined as to best fit the measured or theoretical curves and are used in calculating the value of drain current as a function of gate-to-source voltage and drain-to-source voltage, without any interpolation in actual circuit simulation. The required storage for the coefficients is minimal, the fitting is excellent, and the computational efficiency improves by a factor of up to eight over the SPICE simulation in the DC transfer curve generation.
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Fault diagnosis in combinational digital circuits using a backtrack algorithm to generate fault location hypotheses
- Author(s): S.J. Sangwine
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p.
247
–252
(6)
A backtrack algorithm for the generation of fault location hypotheses in combinational digital circuits is presented. The algorithm uses the results of applied tests and works back from incorrect circuit outputs to generate a list of possible single and/or multiple faults. Suggestions are given for refining the list by selecting probing measurements and by computing the intersection of more than one list resulting from multiple tests.
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Fast multidimensional discrete hartley transform using fermat number transform
- Author(s): S. Boussakta and A.G.J. Holt
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p.
253
–257
(5)
It is shown that by using an index mapping scheme, the multidimensional discrete Hartley transform can be changed into convolutions that can be calculated very efficiently via the Fermat number transform. Compared with existing algorithms, the number of multiplications is reduced by a factor of 8 to 20, at the expense of a slight increase in the number of shift and add operations, that are assumed to be simpler than multiplications.
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