IEE Proceedings E (Computers and Digital Techniques)

IEE Proceedings E (Computers and Digital Techniques)

Online ISSN 2053-7948
Print ISSN 0143-7062

Published from 1980-1993, IEE Proceedings E contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

This journal was previously known as IEE Journal on Computers and Digital Techniques 1978-1979. ISSN 0140-1335. more..

This journal was previously known as Proceedings of the Institution of Electrical Engineers 1963-1979. ISSN 0020-3270. more..

This publication is continued by IEE Proceedings - Computers and Digital Techniques 1994-2006. ISSN 1350-2387. more..

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Cellular logic bus arbitration
- Author(s): E.D. Adamides ; P. Iliades ; I. Argyrakis ; Ph. Tsalides ; A. Thanailakis
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- p. 289 –296 (8)
  The functional and VLSI design of a novel one-of-N bus arbitration circuit for a time-shared bus-interconnected multiprocessor system is presented. The proposed system is a multilevel, hierarchical, two-bit cellular processor structure. The arbitration protocol of rotating priority has been customised to produce a hierarchical, fairness-oriented, rotating-priority protocol that guarantees efficient and deadlock-free time sharing of the bus, with better complexity measures compared to both rotating- and unequal-priority protocols.
Minimising the energy of active contour model using a Hopfield network
- Author(s): C.-T. Tsai ; Y.-N. Sun ; P.-C. Chung
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- p. 297 –303 (7)
  Active contour models (snakes) are commonly used for locating the boundary of an object in computer vision applications. The minimisation procedure is the key problem to solve in the technique of active contour models. In this paper, a minimisation method for an active contour model using Hopfield networks is proposed. Due to its network structure, it lends itself admirably to parallel implementation and is potentially faster than conventional methods. In addition, it retains the stability of the snake model and the possibility for inclusion of hard constraints. Experimental results are given to demonstrate the feasibility of the proposed method in applications of industrial pattern recognition and medical image processing.
Testing check bits at no cost in RAMs with on-chip ECC
- Author(s): P. Ramanathan ; K.K. Saluja ; M. Franklin
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- p. 304 –312 (9)
  The paper addresses the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults while the information bits are being tested, without any increase in the length of the test sequence. Further, the parity-check matrices are such that there is no loss in error-correction capabilities, and there is no penalty in the worst-case delay of the error-correcting logic.
Multilevel logic synthesis for PAL devices
- Author(s): M. Pearce
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- p. 313 –319 (7)
  A system has been developed to perform multilevel logic synthesis onto PALs for designs that will not fit in two-level sum of products form. The procedure is based upon the application of technology dependent selective collapse algorithms on a multilevel circuit. The multilevel circuit may be obtained using a number of different synthesis strategies. The packages have been implemented in C and added to SIS, the sequential synthesis system developed at Berkeley. Results compare favourably with the best previous system known.
Trade-offs in developing fault tolerant software
- Author(s): N.H. Vaidya ; A.D. Singh ; C.M. Krishna
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- p. 320 –326 (7)
  Design diversity has emerged as a powerful mechanism for incorporating software fault tolerance in ultra-reliable systems. In this paper we study the trade-offs available during the development process of fault-tolerant software employing the recovery block approach [2]. When the total available testing time is bounded, our analysis determines how appropriately to allocate testing time to the various redundant modules that make up the fault tolerant system so as to maximise its reliability. This requires a study of the interactions between the various modules in the software system. For example error coverage and the false alarm probability of acceptance test in the recovery block scheme may be interrelated and it may not be possible to simultaneously improve both. Hence there exists a trade-off between acceptance test coverage and false alarm probability. The impact of such trade-offs on system reliability is also studied.

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IEE Proceedings E (Computers and Digital Techniques)

Volumes & issues:

Volume 140 (1993)

Volume 139 (1992)

Volume 138 (1991)

Volume 137 (1990)

Volume 136 (1989)

Volume 135 (1988)

Volume 134 (1987)

Volume 133 (1986)

Volume 132 (1985)

Volume 131 (1984)

Volume 130 (1983)

Volume 129 (1982)

Volume 128 (1981)

Volume 127 (1980)

Latest content

Cellular logic bus arbitration

Minimising the energy of active contour model using a Hopfield network

Testing check bits at no cost in RAMs with on-chip ECC

Multilevel logic synthesis for PAL devices

Trade-offs in developing fault tolerant software

Most viewed content for this Journal

Most cited content for this Journal