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IEE Proceedings E (Computers and Digital Techniques)

Volume 137, Issue 2, March 1990

Volumes & issues:

Volume 137, Issue 2

March 1990

Properties of low augmentation level T-codes
  • Author(s): G.R. Higgie  and  A.G. Williamson
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 129 –132
  • DOI:  10.1049/ip-e.1990.0012
  • Type: Article
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  • p. 129 –132 (4)
    Initial investigations of the re-synchronisation properties of fifth augmentation level, variable length, self-synchronising T-codes are described. It has been found from simulation studies that within the fifth augmentation level family there are considerable differences in the resynchronisation delay statistics of individual code sets, with some code sets consistently outperforming others with the same codeword length distribution. Furthermore, the code sets with the shortest average re-synchronisation delays are generally those with the shortest average code-word length (i.e. the most efficient). The coding efficiency of these code sets has been found to be within 1% of the efficiency of a Huffman code optimised for the particular information source.
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Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy
  • Author(s): Y.-N. Shen  and  F. Lombardi
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 133 –136
  • DOI:  10.1049/ip-e.1990.0013
  • Type: Article
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  • p. 133 –136 (4)
    In this paper, a new approach to repairability/unrepairability detection for VLSI memory chips with redundancy is presented. An heuristic, yet efficient approach, is proposed. New conditions for detection are presented and fully analysed. These are based on a more accurate estimation of the regions of repairability and unrepairability. The main benefit of this approach is its practicality with respect to fast execution time and the improved ability to diagnose a VLSI redundant memory before the generation of the repair-solution. A new repair algorithm which utilizes a ternary tree approach is also presented.
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Fast algorithms for short prime length fast biased polynomial transforms
Fast transform decoding of nonsystematic reed-solomon codes
Evaluation of real time adaptive noise cancelling algorithms as implemented using a digital signal processor chip
  • Author(s): M.L. Wagner  and  K.W. Current
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 144 –150
  • DOI:  10.1049/ip-e.1990.0016
  • Type: Article
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  • p. 144 –150 (7)
    Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realisation of realtime adaptive noise cancellers with single chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application. Considered are stochastic gradient lattice and least squares lattice algorithms. For the purpose of comparison, the stochastic gradient transversal algorithm is also evaluated. Their performances under a variety of signal and noise excitations are summarised and compared in terms of operating rates and misadjustments.
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Algorithm for forming relationships between objects in a scene
Testing of data paths in VLSI arrays
  • Author(s): Choi Yoon-Hwa
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 154 –158
  • DOI:  10.1049/ip-e.1990.0018
  • Type: Article
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  • p. 154 –158 (5)
    An important issue in VLSI array design is how to test switches and data links in an array. In the paper, the authors present a ‘divide-and-conquer’ technique for testing data paths in VLSI arrays. The data paths including registers, switches and data links are tested in parallel by applying test patterns from the outside. The fault-free paths identified divide the array into smaller subarrays with fault-free boundaries so that testing can be done recursively. Fault masking due to switch failures is examined. A sufficient condition to avoid fault masking is obtained.
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Efficient approach to embed binary trees in 3-D rectangular arrays
  • Author(s): S. Latifi  and  A. El-Amawy
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 159 –163
  • DOI:  10.1049/ip-e.1990.0019
  • Type: Article
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  • p. 159 –163 (5)
    The complete binary tree has long been known to support important applications. This paper presents an efficient embedding of a complete binary tree in a 3-D rectangular array. The array hosting the binary tree is called the host, and the binary tree is referred to as the guest. The scheme is modular and high level trees are made of low level trees inductively. It is shown that all PEs (except one) of the host array may be utilised in embedding a k-level complete binary tree. The dilation (maximum length of an edge in the guest graph in terms of the number of edges in the host graph) is kept as low as possible by using building blocks, which allow tree embedding, with dilation of two at most occurring between leaf nodes and their parents where the message traffic is minimum. Upperbounds on propagation delay are reduced from O(2k/2 to O(2k/3) as a result of the use of the third dimension. Results are compared with those dealing with 2-D layouts. As discussed, these bounds are the best known to date for structures with practically implementable dimensionality.
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Automated synthesis of combinational circuits by cascade networks of multiplexers
  • Author(s): R.K. Gorai  and  A. Pal
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 137, Issue 2, p. 164 –170
  • DOI:  10.1049/ip-e.1990.0020
  • Type: Article
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  • p. 164 –170 (7)
    Knowledge of the advantages of realising VLSI circuits in cellular form have stimulated research in the synthesis of digital circuits by using cellular networks of suitable gates. The cascade network is a special kind of cellular form with a very simple interconnection structure. This paper is concerned with the synthesis of combinational circuits using a cascade of 2-input multiplexer units. A multiplexer unit has been taken as the building block because of its versatility and possibility of use as a universal logic module. Based on the characterising parameters called ‘ratio parameters’, an algorithm has been developed to synthesise a given Boolean function by a cascade of two input multiplexers, if realisable. The algorithm is easy to implement on a computer and a program implementing the algorithm in c-language has been developed, thereby allowing automated synthesis. This is essential when the complexity of the digital circuits is high. Both completely specified and incompletely specified functions have been considered.
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