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IEE Proceedings E (Computers and Digital Techniques)

Volume 136, Issue 5, September 1989

Volumes & issues:

Volume 136, Issue 5

September 1989

Special section on associative processors and memories
Neural networks and conditional association networks. common properties and differences
Content-addressable mass memories
Flag-algebra: a new concept for the realisation of fully parallel associative architectures
  • Author(s): D. Tavangarian
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 357 –365
  • DOI:  10.1049/ip-e.1989.0048
  • Type: Article
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  • p. 357 –365 (9)
    The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented each by a flag in a flagvector. The position of a flag in the flagvector is defined by the transformation and corresponds to the value of the transformed word. To obtain parallelism for various operations, the flags of the flagvector will be processed simultaneously. The result of these operations will also be flags. They can be retransformed to word-oriented data. A new algebra called flag-algebra to investigate operations on the flagvector will be introduced. This algebra is the isomorph to the set-theory and Boolean algebra. The most important axioms and laws of calculation in this algebra will be described. They can be seen as a substantial basis for the development of flag-oriented hardware systems. Based on this algebra, the architecture of an associative monoprocessor will be presented to process arithmetical as well as complex search operations in parallel. Furthermore, some languages adequate for this architecture and the performance of the processor will be discussed.
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Architectures for testability and fault tolerance in content-addressable systems
  • Author(s): K.E. Grosspietsch
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 366 –373
  • DOI:  10.1049/ip-e.1989.0049
  • Type: Article
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  • p. 366 –373 (8)
    For the next computer generation, which may have extensive artificial intelligence properties, the use of associative processing may have increasing importance. Here, VLSI technologies especially can stimulate the development of larger content-addressable memories (CAMs). The problem of production yield and component failure, as well as that of efficient testability, will be as important as for other computer components. Therefore, compared with conventional random access memory, the more complicated memory structure of CAMs has greater problems of testing and reconfigurability. In the paper, the problems of testability and fault tolerance in different CAMs and content-addressable processor systems are discussed.
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Design of an associative processor array
Content-addressable memories applied to execution of logic programs
  • Author(s): J.C.D.F. Ribeiro ; C.D. Stormon ; J.V. Oldfield ; M.R. Brule
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 383 –388
  • DOI:  10.1049/ip-e.1989.0051
  • Type: Article
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  • p. 383 –388 (6)
    The paper describes a number of techniques for using content-addressable memory to speed up the execution of logic programs for both single and multiple processor implementations. The techniques shown allow for significant speed-ups in unification, clause selection, branch switching, variable handling and garbage collection. For multiple processor implementations, the literal ordering and environment join algorithms are also improved. In addition to the speed improvements, some simplification of software results from performing indexing operations in content-addressable memory.
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Fault tolerance of neural associative memories
Control of manipulators by neural networks
Windmill pn-sequence generators
  • Author(s): B.J.M. Smeets  and  W.G. Chambers
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 401 –404
  • DOI:  10.1049/ip-e.1989.0054
  • Type: Article
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  • p. 401 –404 (4)
    A windmill generator is a high-speed sequence generator capable of producing blocks of v consecutive symbols in parallel. It consists of v feedback-shift registers linked into a ring. The sequences are identical to those produced by a linear feedback-shift register with feedback polynomial of the special (‘windmill’) form f(t) = α(tv) − tLβ(t−v), where α(t) and β(t) are polynomials of degree less than L/v. Here L (relatively prime to v) is the degree of the polynomial, and is also the sum of the lengths of the registers making up the windmill. The connections of the windmill generator are directly specificed by the coefficients of α(t) and β(t). The polynomial f(t) must be primitive if the output sequence is to be of maximal period. We have devised a search for windmill polynomials over the binary field that can generate sequences of period 2L − 1 in blocks of size v = 4, 8, and 16, for L ranging over the odd values from 7 to 127. When L ≡ ±3 mod 8, no irreducible windmill polynomials at all were found. For the other odd values of L, primitive windmill polynomials seem to occur about twice as frequently as would be expected from probabilistic considerations, so that they are in fact very common. For such values of L, roughly 2/L of all windmill polynomials with given v appear to be primitive.
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Pruned-trellis search technique for high-rate convolutional codes
  • Author(s): J. Sun ; I.S. Reed ; H.E. Huey ; T.K. Truong
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 405 –414
  • DOI:  10.1049/ip-e.1989.0055
  • Type: Article
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  • p. 405 –414 (10)
    A new method to search for high-rate convolutional codes is achieved by means of a pruned trellis. This makes possible a reduced search procedure that can not be accomplished by standard methods. This new search technique makes use of the concept of the expanded column distance function of a convolutional code. By use of this search procedure, codes are found with an optimum distance profile followed by a maximisation of dfree. A number of systematic convolution al codes of high rates 3/4, 4/5, 5/6, 6/7, and 3/5 are found and listed in this paper.
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Bidirectional ring-based termination detection algorithms for distributed computations
Performance analysis of queuing networks with end-to-end window flow control
  • Author(s): J.S. Wu  and  W.C. Chan
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 423 –429
  • DOI:  10.1049/ip-e.1989.0057
  • Type: Article
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  • p. 423 –429 (7)
    The paper deals with queuing networks with window flow control and group arrivals. By using the method of entropy maximisation, an equivalent arrival process is obtained and is then applied to study queuing networks. We consider the networks of single-server nodes in both continuous and discrete time, and multiple exponential-server nodes in continuous time. Numerical results are obtained for the mean number of packets at the nodes, the server utilisations and the network throughput. It is shown that the calculated results agree favourably with the simulation results.
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Detection of stuck-at and bridging faults in reed—muller canonical (RMC) networks
  • Author(s): T. Damarla  and  M. Karpovsky
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 430 –433
  • DOI:  10.1049/ip-e.1989.0058
  • Type: Article
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  • p. 430 –433 (4)
    Boolean function realisations by Reed—Muller networks have many desirable properties in terms of testability [11]. In the paper it is shown that there exists a single set of test patterns which would detect all single stuck-at and all single bridging (short-circuit) faults in Reed-Muller networks, and the number of test patterns is shown to be at most 3n + 5, where n is the number of input variables in the function. In the case of networks with k outputs, where k ≤ 2n, the number of test patterns required to detect all single stuck-at and all single detectable bridging faults (both AND and OR) is also shown to be 3n + 5.
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Test generation of C-testable array dividers
  • Author(s): C.L. Wey  and  S.M. Chang
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 434 –442
  • DOI:  10.1049/ip-e.1989.0059
  • Type: Article
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  • p. 434 –442 (9)
    With respect to the regular and iterative structure of iterative logic arrays (ILAs), the C-testable design that can be tested with a set of constant length irrespective of the circuit size has been presented. In the paper the concept of C-testability developed for ILAs is applied to the design of C-testable array dividers. The results show that the proposed nonrestoring and restoring array dividers are C-testable and can be fully tested using only 20 and 40 test patterns, respectively, irrespective of the array size. The innovative feature of the proposed test-generation scheme is that the generated patterns are constructed by repetitive and simple patterns that can be easily produced by a set of labels. Algorithms that generate the test patterns and expected outputs are also provided in detail.
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Very fast reduction machine for functional programming without variables
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters
Integrating voice and data services in token rings
  • Author(s): A. Pattavina
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 136, Issue 5, p. 456 –463
  • DOI:  10.1049/ip-e.1989.0062
  • Type: Article
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  • p. 456 –463 (8)
    An access protocol for efficient voice-data integration in a token ring network is described. It is based on the adoption of a variable size of voice packet that is determined by the actual load conditions. To take into account efficiency problems of token rings related to the ratio of average packet size and ring latency, two versions of the access protocol are described that adopt different token releasing strategies, namely, single-token and multiple-token. In each of these protocols, voice and data users are serviced according to a specific priority scheme, which bounds voice packet delay and guarantees a minimum data bandwidth fairly allocated among data stations.
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