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1887

IEE Proceedings E (Computers and Digital Techniques)

Volume 134, Issue 2, March 1987

Volumes & issues:

Volume 134, Issue 2

March 1987

Test generation for digital circuits described by means of register transfer languages
  • Author(s): E. Villar  and  S. Bracho
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 69 –77
  • DOI:  10.1049/ip-e.1987.0012
  • Type: Article
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  • p. 69 –77 (9)
    In this paper, we propose systematic procedures for generating the test sequence for digital systems described by means of procedural register transfer languages. Faults in the data unit (data faults) and in the control unit (control faults) will require different techniques for their detection. For the data unit, a graph representing the data flow, the transfer graph, is proposed. Techniques for justifying and sensitising data faults are described. For the control unit we study the problem of its identification by using distinguishing sequences for its states. Testing of both units can be overlapped to reduce the length of the test sequence for the whole circuit.
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Book review: Advanced Digital Information Systems
Fault diagnosis in Beněs switching networks
Techniques for implementing two-dimensional wafer-scale processor arrays
  • Author(s): C. Jesshope  and  L. Bentley
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 87 –92
  • DOI:  10.1049/ip-e.1987.0015
  • Type: Article
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  • p. 87 –92 (6)
    This paper describes some of the techniques that are being used to implement a two-dimensional wafer-scale processor array. Manufacturing defects on the wafer are tolerated by using hierarchical redundancy. This strategy employs programmable links at the highest sub-system level to ensure good electrical isolation against gross defects, while lower down in the hierarchy, transistor switches are used to reduce the overall test and programming overhead.This technique enables a logical two-dimensional array of cells to be efficiently mapped onto a larger but flawed array. A row-configuring algorithm is proposed and simulation results are given for 8 × 8 and 16 × 16 arrays by assuming a uniform distribution of defects across the wafer. An empirical yield model and a novel programmable link are also described.
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Graphical method for the conversion of minterms to Reed-Muller coefficients and the minimisation of exclusive-OR switching functions
  • Author(s): A. Tran
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 93 –99
  • DOI:  10.1049/ip-e.1987.0016
  • Type: Article
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  • p. 93 –99 (7)
    A graphical method extended from a folding technique developed by Wu et al. is used to convert the minterms of a switching function to the coefficients of its Reed-Muller polynomial with fixed polarity. The conversion starts from a Karnaugh map and results in a Reed-Muller coefficient map. An algorithm which attempts to find a minimal exclusive-OR realisation for the switching function in mixed polarity by grouping the Reed-Muller coefficient map is presented. The graphical method of converting minterms to Reed-Muller coefficients and the minimisation algorithms are also applied to incompletely specified functions.
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Book review: Local Area Network Design
Digital image registration by phase correlation between boundary maps
Algorithm to detect reconvergent fanouts in logic circuits
  • Author(s): M.W. Roberts  and  P.K. Lala
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 105 –111
  • DOI:  10.1049/ip-e.1987.0019
  • Type: Article
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  • p. 105 –111 (7)
    Testability measures have been advocated by many authors as aids in the designing and testing of logic circuits. These have been shown to be inaccurate for circuits which contain reconvergent fanouts. An algorithm is presented which will detect all sources of reconvergence in a circuit by processing a normal textual circuit description. As well as identifying all the gates at which reconvergence occurs, the reconvergent sites, the algorithm lists all the fanout nodes that reconverge at each of these sites. The automatic detection of reconvergence can be used for improving the testability analysis of circuits containing such fanouts. This algorithm is also being used as the basis of an analysis which identifies the undetectable faults in a circuit.
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Algorithm for obtaining a self-synchronising M-ary code enabling data compression
  • Author(s): M.D. Mirković  and  I.S. Stojanović
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 112 –118
  • DOI:  10.1049/ip-e.1987.0020
  • Type: Article
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  • p. 112 –118 (7)
    An algorithm for obtaining a self-synchronising M-ary code (M ≥ 2) enabling the compression of data from a stationary discrete memoryless source is proposed. After presenting the code algorithm, its properties are analysed and the implementation of the code is described. The code proposed is compared to the Huffman code with regard to the average code-word length, the possibility of self synchronisation and the complexity of hardware realisation. Although for certain sources the code proposed is equal or nearly equal to the Huffman code regarding data compression, in general it is less efficient. However, its property of being self synchronising, and its relatively simple hardware realisation, make this code valuable for practical applications.
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Parallel image-processing system based on the TMS32010 digital signal processor
  • Author(s): K.N. Ngan ; A.A. Kassim ; H.S. Singh
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 134, Issue 2, p. 119 –124
  • DOI:  10.1049/ip-e.1987.0021
  • Type: Article
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  • p. 119 –124 (6)
    A parallel image processor (PIP) consisting of eight Texas Instruments TMS32010 digital signal processors is described. The architecture is designed for image-processing applications and two common pattern-recognition algorithms, i.e. edge detection followed by thinning are implemented achieving a total processing time of less than one second for a 256 × 256 pixel image. The advantages and limitations of using the TMS32010 as a fast signal processor are described. Problems encountered in programming the parallel processors and ways to overcome them are highlighted.
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