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Volume 133
Issue 2
IEE Proceedings E (Computers and Digital Techniques)
Volume 133, Issue 2, March 1986
Volumes & issues:
Volume 133, Issue 2
March 1986
Spectral testing of circuit realisations based on linearisations
- Author(s): E. Eris and J.C. Muzio
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 73 –78
- DOI: 10.1049/ip-e.1986.0007
- Type: Article
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Fault-detection techniques using data compression have evolved during the last few years. Two of these involve syndrome testing and spectral-coefficient testing, which are closely related to each other. It is shown in the paper that, for combinational circuits designed using a linearisation method proposed by a number of authors, it is always possible to cover all single stuck-at faults using a linearisation signature that consists of m + 1 spectral coefficients (m < n, the number of input variables). It is also shown that the linearisation signature provides some coverage against multiple faults in the circuit.
Processor failure recovery for a resource sharing algorithm
- Author(s): I.A. Newman ; R.P. Stallard ; M.C. Woodward
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 79 –86
- DOI: 10.1049/ip-e.1986.0008
- Type: Article
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With the increase in popularity of distributed computer systems, the reliability of the system as a whole is becoming more important. A recently published combined resource sharing algorithm showed how the atomic operations required for resource management in a closely coupled multiprocessor system could be provided. The paper describes a recovery system that may be incorporated within the earlier algorithm to enable continued and correct operation of the system despite the failure of one or more component processors. A distributed simulation of the recovery mechanism is described and results from simulation runs are presented.
Parallel algorithm for shortest paths
- Author(s): R.K. Ghosh and G.P. Bhattacharjee
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 87 –93
- DOI: 10.1049/ip-e.1986.0009
- Type: Article
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An algorithm for finding a shortest path between each pair of nodes of a positive arc weighted graph on a shared memory model of a single instruction-stream multiple data-stream computer is proposed. The time complexity of the algorithm is of O(log d . log n), where d and n denote the diameter and the number of nodes of the graph, respectively. At most, O(n3) processors are required to achieve this time bound.
Secret-hardware public-key cryptography
- Author(s): S.C. Kak
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 94 –96
- DOI: 10.1049/ip-e.1986.0010
- Type: Article
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The paper presents the concept of secret-hardware public-key (SHPK) cryptography which allows the design of efficient systems, provided there exists a trusted central authority to generate key pairs. A realisation of a SHPK system based on exponentiation is presented.
Technical memorandum. Digital linear transducer using a dynamic RAM
- Author(s): J.G. Lacy and M.P. Kennedy
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 97 –99
- DOI: 10.1049/ip-e.1986.0011
- Type: Article
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A dynamic RAM can form the basis of a low-cost digital position sensor. The theory of operation of such a device is presented, and experimental results for a prototype DRAM-based transducer are discussed.
APL: an effective design language
- Author(s): M. van Sinderen ; C. Huijs ; G.A. Blaauw
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 133, Issue 2, p. 100 –104
- DOI: 10.1049/ip-e.1986.0012
- Type: Article
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The paper describes the use of APL (a programming language) for the specification of a hardware architecture, the description of an initial implementation algorithm, its verification and controlled transformation to a logic design. Because of its power of expression, APL can be used effectively in each of these design domains. The APL interpreter turns any description into an executable prototype. Such a prototype is a powerful tool in the management and execution of a design; it clarifies design choices and assures the logical correctness of the product. This computer-aided-design process, which is illustrated by the design of the front end of a logic analyser, is useful for a variety of design situations, such as LSI/VLSI and computer design.
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