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IEE Proceedings E (Computers and Digital Techniques)

Volume 131, Issue 6, November 1984

Volumes & issues:

Volume 131, Issue 6

November 1984

Microprogrammable sequential controller
  • Author(s): D.M. Divan ; G.C. Hancock ; G.S. Hope ; T.H. Barton
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 131, Issue 6, p. 201 –208
  • DOI:  10.1049/ip-e.1984.0039
  • Type: Article
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  • p. 201 –208 (8)
    The architecture and design of a high-performance general-purpose microprogrammable sequential controller are presented. Conventional logic controllers are limited by speed, memory requirements or flexibility and programming ease. The requirements of a basic sequential controller are identified, and a memory segmentation technique is proposed for efficient data structuring. A parallel-architecture sequential controller is designed so that it is both fast and memory efficient. The new controller has a fixed hardware and is microprogrammable through firmware modification. It is especially designed for complex high-speed sequential controllers requiring large I/O capabilities.
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Design and evaluation of the event-driven computer
  • Author(s): F.S. Wong  and  M.R. Ito
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 131, Issue 6, p. 209 –222
  • DOI:  10.1049/ip-e.1984.0040
  • Type: Article
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  • p. 209 –222 (14)
    This paper describes a new design methodology for a class of next-generation computers. Our proposal, the event-driven computer (EDC), is primarily a data-driven heterogeneous system which is supplemented with control-driven activities; such a combined approach is aimed at extracting the advantages of both the ‘pure’ data-driven and control-driven systems while alleviating their shortcomings. Compared to other similar designs EDC has the advantages of a better resource utilisation, array processing capabilities and a higher speed range. The hardware architecture, language features and performance evaluation are discussed. A recently developed loop-structured interconnection network is modified for this application; with a configuration of 64 loops, it can connect up to approximately 400 processors, and hence an execution speed of more than 1000 MOPS can be obtained.
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Hardware for real-time image processing
  • Author(s): C.D. McLlroy ; R. Linggard ; W. Monteith
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 131, Issue 6, p. 223 –229
  • DOI:  10.1049/ip-e.1984.0041
  • Type: Article
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  • p. 223 –229 (7)
    The system described here is a real-time edge detector for use in image processing. The edge-detection algorithm is a 2 × 2 Roberts product, thresholded with a function of the local average brightness. The hardware is designed to work at 10 MHz pixel rate, and will accommodate images of 512 × 512 pixels at 25 frames/s with noninterlaced video, or of up to 512 × 290 pixels with interlaced scanning. The hardware is pipelined and paralleled to achieve the required speed. The output from the system is a one-bit-per-pixel edge picture. This is transferred directly into the memory of the host computer for further processing.
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VLSI—evolution or revolution
Conference report. 14th IEEE international symposium on multiple-valued logic
Erratum: Editorial

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