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Volume 129
Issue 3
IEE Proceedings E (Computers and Digital Techniques)
Volume 129, Issue 3, May 1982
Volumes & issues:
Volume 129, Issue 3
May 1982
Lifetime analyses of error-control coded semiconductor RAM systems
- Author(s): R.M.F. Goodman and R.J. Mceliece
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 81 –85
- DOI: 10.1049/ip-e.1982.0017
- Type: Article
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p.
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The paper is concerned with developing quantitative results on the lifetime of coded random-access semiconductor memory systems. Although individual RAM chips are highly reliable, when large numbers of chips are combined to form a large memory system, the reliability may not be sufficiently high for the given application. In this case, error-correction coding is used to improve the reliability and hence the lifetime of the system. Formulas are developed which will enable the system designer to calculate the improvement in lifetime (over an uncoded system) for any particular coding scheme and size of memory. This will enable the designer to see if a particular memory system gives the required reliability, in terms of hours of lifetime, for the particular application. In addition, the designer will be able to calculate the percentage of identical systems that will, on average, last a given length of time.
Detection and location of errors by linear inequality checks
- Author(s): M. Karpovsky
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 86 –92
- DOI: 10.1049/ip-e.1982.0018
- Type: Article
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p.
86
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Problems of error detection and error location in programs or specialised devices computing values of real functions are considered. Systems of linear inequality checks are used for error detection and error location. Theorems are given for solving the problem of the error-detecting and locating capabilities of memoryless and memory-aided decoding procedures based on linear-inequality checks.
Statistical efficiency of universal logic elements in realisation of logic functions
- Author(s): A.M. New
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 93 –99
- DOI: 10.1049/ip-e.1982.0019
- Type: Article
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93
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The specification of standard logic elements with which any combinatorial or storage requirement can be realised is briefly reviewed, such elements ranging from simple NAND and NOR Boolean gates through to universal-logic-elements of several forms. Here we specifically consider for the first time a comprehensive range of the latter elements, and give the full statistics of the number of elements required to realise a range of duties in comparison with NAND and NOR gates.
IEE East Midland Electronics & Control Section: Chairman's address. Picture coding
- Author(s): R.J. Clarke
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, page: 100 –100
- DOI: 10.1049/ip-e.1982.0020
- Type: Article
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100
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Signal classification for automatic industrial inspection
- Author(s): C.B. Chittineni
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 101 –106
- DOI: 10.1049/ip-e.1982.0021
- Type: Article
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p.
101
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Details of a system designed to inspect web-type products are presented. The sensing device used is a laser scanner, and a brief description of the scanner is given. A set of bandpass filters is proposed as feature extracters. The required characteristics of the filters are determined through digital simulation, using feature selection methods. The linear classifier is designed from a set of training signals. Contextual information is used in the classification of signals into good product or into various defective categories. In addition, results of a study on inspection of magnetic tapes and abrasive sheets are described.
Realisation of multithreshold threshold-logic gates using charge-coupled devices
- Author(s): P.D. Picton
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 107 –110
- DOI: 10.1049/ip-e.1982.0022
- Type: Article
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p.
107
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A threshold logic gate is described which uses as its core a charge-coupled device. It is shown that the CCD is suitable for this application because of its ability to (a) quantise charge input to a gate, (b) add charge packets from different gates, and (c) permit conditional charge overflow to occur. The peripheral circuitry employs compatible MOSFET circuits, so that the entire gate can be made in integrated circuit form. The gate is voltage programmbale.
Tabular implementation for the ternary functions of two variables
- Author(s): A. Lloris ; A. Cobo ; A. Prieto
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 111 –118
- DOI: 10.1049/ip-e.1982.0023
- Type: Article
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111
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A tabular procedure is presented for the implementation of the ternary functions of two variables, based on a previous classification, as permutations, of ternary functions of two variables. The synthesis for any one of the 19 683 ternary functions of two variables may be obtained from the synthesis given for only 84 functions — the canonical functions of 84 equivalence classes obtained in the above classification. For the synthesis, only 2-input AND and OR gates (besides unary operators) are used. This method compares favourably with standard methods and the whole procedure may easily be programmed to be executed by computers.
M/G/1 queue analysis via the inverse Poisson transform
- Author(s): M.H. Ackroyd
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 119 –122
- DOI: 10.1049/ip-e.1982.0024
- Type: Article
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119
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The Poisson transform arises at several places in the theory of the M/G/1 queue, in the theory of photoelectricity and in signal theory. This paper discusses the problem of numerical inversion of the Poisson transform, with emphasis on its application to queueing problems.
Distributed multiple-microprocessor network
- Author(s): C.C. Lau and H.F. Li
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, p. 123 –130
- DOI: 10.1049/ip-e.1982.0025
- Type: Article
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123
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The design of a distributed multiprocessor system has received much attention in recent years. With the advent of technology in LSI and VLSI, a cost-effective multiple-microprocessor module can be designed. The module can be employed as a basic element in configuring a distributed system. Several problems are to be solved in such a design: (a) internal structure of each module, (b) handshake between modules, (c) information interchange via distributed mailbox, (d) distributed timing and control, and (e) distributed priority resolving and deadlock detection. In this paper, these problems will be discussed and experimental solutions proposed. A simple performance analysis is also included.
Data Structure Techniques
- Author(s): J. Hollom
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, page: 132 –132
- DOI: 10.1049/ip-e.1982.0026
- Type: Article
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132
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Minicomputers: a Reference Book for Engineers, Scientists and Managers
- Author(s): R. Reissner
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, page: 132 –132
- DOI: 10.1049/ip-e.1982.0027
- Type: Article
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p.
132
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Erratum: Fast transform procedure for the generation of near-minimal covers of Boolean functions
- Author(s): Ph.W. Besslich and P. Pichlbauer
- Source: IEE Proceedings E (Computers and Digital Techniques), Volume 129, Issue 3, page: 132 –132
- DOI: 10.1049/ip-e.1982.0028
- Type: Article
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