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IEE Proceedings E (Computers and Digital Techniques)

Volume 128, Issue 4, July 1981

Volumes & issues:

Volume 128, Issue 4

July 1981

DEFASM: a microprogram meta-assembler with semantic capability
  • Author(s): M. Mezzalama ; P. Prinetto ; S. Romani
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 128, Issue 4, p. 133 –142
  • DOI:  10.1049/ip-e.1981.0026
  • Type: Article
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  • p. 133 –142 (10)
    A microprogram assembler which can assemble code for any user-defined target machine, i.e. a metamicroassembler, is described. Its most important feature is a definition phase where a description of the actual microinstruction set is given once for all, using a simple definition language. Within this definition phase, simple semantic controls may be introduced to facilitate the detection of errors that microprogram writers tend to make when the target machine has a high degree of parallelism, i.e. when long microinstructions are used.
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Classification under permutations of the ternary functions of two variables
  • Author(s): A. Lloris  and  J. Velasco
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 128, Issue 4, p. 143 –148
  • DOI:  10.1049/ip-e.1981.0027
  • Type: Article
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  • p. 143 –148 (6)
    The paper presents a classification of the ternary functions of two variables by application of the permutation group either to the input variables or to the output, and by the interchange of the input variables. A set of invariants for the characterisation of the equivalence classes resulting from this classification is introduced, and also an algorithm for their calculation. As an alternative characterisation, the canonical function for each equivalence class is defined. The algorithm for the calculation of the invariants allows us to obtain the transformations that lead from a given function to any other function in its equivalence class. The classification procedure allocates each of the 19683 ternary functions of two variables to one of 84 equivalence classes; these are given, indicating the invariants and the canonical function corresponding to each.
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User-oriented architecture
  • Author(s): E. Luque  and  A. Ripoll
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 128, Issue 4, p. 149 –154
  • DOI:  10.1049/ip-e.1981.0028
  • Type: Article
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  • p. 149 –154 (6)
    With a dynamically microprogrammable computer, the user has the opportunity to tune the architecture to a given application in order to minimise its execution time. The program must be analysed to identify all the instruction sequences/segments, loops and functionally equivalence sequences) which can constitute new instructions. A set of parameters are associated with every sequence for selecting those sequences which maximise the time saving in the execution of the program. In the selection process, two different methods have been developed; the first is based on integer linear programming and provides the best solution; the second consists of a linear iterative algorithm, which has the advantage of being less time consuming
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Hardware evaluation of mathematical functions
  • Author(s): M.R.D. Rodrigues ; J.H.P. Zurawski ; J.B. Gosling
  • Source: IEE Proceedings E (Computers and Digital Techniques), Volume 128, Issue 4, p. 155 –164
  • DOI:  10.1049/ip-e.1981.0029
  • Type: Article
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  • p. 155 –164 (10)
    The paper presents a family of algorithms for evaluating the elementary mathematical functions including division, sine, cosine, tangent, arctangent, logarithm, exponential and square root. The algorithms are based on continued products and continued sums, and generate the sum on a 2-bit-at-a-time basis. The only operations required are shifting, adding, subtracting and recall of prestored constants. Consequently, the method is suitable for hardware implementation, and two designs are presented. The faster design can generate a 64-bit result in under 1 μs for most of the functions, and under 2 μS for the remainder, when using ECL technology of the F100K type. The other design is based on a pipelined structure and is approximately 40% slower and cheaper. The performance of both designs compares favourably with that of a hardwired polynomial evaluation based on Homer's scheme when using a 300 ns 64- by 64-bit multiplier. Such a design is between 35% and 130% slower than the pipelined version depending upon the function evaluated, yet only 30% cheaper.
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Interactive image-processing software for a microcomputer
Computer Arithmetic: Benchmark Papers in Electrical Engineering and Computer Science, 21
Digital Signal Processing
Advanced Techniques for Microprocessor Systems
Coded Character Sets, History and Development
Computer System Reliability
Erratum: Fast polynomial transform and its implementation by computer

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