IEE Proceedings - Computers and Digital Techniques

Volume 153, Issue 5, September 2006

Volume 153, Issue 5

September 2006

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    • Flexible GF(2m) arithmetic architectures for subword parallel processing ASIPs
      Bottom-up approach in automated embedded memory model generation for high-performance microprocessors
      Improving energy-efficiency in high-performance processors by bypassing trivial instructions
      Applying the Handel-C design flow in designing an HMAC-hash unit on FPGAs
      Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning
      Employing pipelined thinning architecture for real-time fingerprint verifier
      Trace cache miss tolerance for deeply pipelined superscalar processors
      System integration by request-driven GALS design

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