IEE Proceedings - Computers and Digital Techniques

Volume 152, Issue 4, July 2005

Volume 152, Issue 4

July 2005

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    • Exploiting temporal loads for low latency and high bandwidth memory
      Topology adaptive network-on-chip design and implementation
      Focalising dynamic value prediction to CPU's context
      Low-power branch target buffer for application-specific embedded processors
      Efficient unified Montgomery inversion with multibit shifting
      Low-power variable-length fast Fourier transform processor
      Selective block buffering TLB system for embedded processors
      Zero-overhead loop controller that implements multimedia algorithms
      Signature-monitoring technique based on instruction-bit grouping

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