IEE Proceedings - Computers and Digital Techniques

Volume 152, Issue 3, May 2005

Volume 152, Issue 3

May 2005

Show / Hide details
    • Architecture description languages for programmable embedded systems
      Clockless circuits and system synthesis
      CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip
      Low-power RT-level synthesis techniques: a tutorial
      Low-power system scheduling, synthesis and displays
      Leakage power analysis and reduction: models, estimation and tools
      Hardware/software cosimulation from interface perspective
      Hardware/software covalidation
      System level validation using formal techniques
      Exploiting defect clustering for yield and reliability prediction
      High-resolution flash time-to-digital conversion and calibration for system-on-chip testing
      Low-cost modular testing and test resource partitioning for SOCs
      Optimisation of on-chip design-for-test infrastructure for maximal multi-site test throughput

Most viewed content for this Journal


Most cited content for this Journal

We currently have no most cited data available for this content.

This is a required field
Please enter a valid email address