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Volume 152
Issue 2
IEE Proceedings - Computers and Digital Techniques
Volume 152, Issue 2, March 2005
Volumes & issues:
Volume 152, Issue 2
March 2005
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- Author(s): B. M. Al-Hashimi
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, page: 113 –113
- DOI: 10.1049/ip-cdt:20059058
- Type: Article
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- Author(s): A. Jantsch and I. Sander
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 114 –129
- DOI: 10.1049/ip-cdt:20045098
- Type: Article
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Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system. Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment. The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs. It is contended that it is of importance for the quality of tools and overall design productivity, which abstraction levels and which primitive operators are provided in a language. However, it is observed that there are various flexible ways to do this, e.g. by way of heterogeneous frameworks, coordination languages and embedding of different MoCs in the same language. - Author(s): P. Pop ; P. Eles ; Z. Peng
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 130 –147
- DOI: 10.1049/ip-cdt:20045069
- Type: Article
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130
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An increasing number of real-time applications are today implemented using distributed heterogeneous architectures composed of interconnected networks of processors. The systems are heterogeneous, not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. Each network has its own communication protocol, each processor in the architecture can have its own scheduling policy, and several scheduling policies can share a processor. In this context, the task of designing such systems is becoming increasingly important and difficult at the same time. The success of such new design methods depends on the availability of analysis and optimisation techniques. Analysis and optimisation techniques for heterogeneous real-time embedded systems are presented in the paper. The authors address in more detail a particular class of such systems called multi-clusters, composed of several networks interconnected via gateways. They present a schedulability analysis for safety-critical applications distributed on multi-cluster systems and briefly highlight characteristic design optimisation problems: the partitioning and mapping of functionality, and the packing of application messages to frames. Optimisation heuristics for frame packing aimed at producing a schedulable system are presented. Extensive experiments and a real-life example show the efficiency of the frame-packing approach. - Author(s): R. Henia ; A. Hamann ; M. Jersak ; R. Racu ; K. Richter ; R. Ernst
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 148 –166
- DOI: 10.1049/ip-cdt:20045088
- Type: Article
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148
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SymTA/S is a system-level performance and timing analysis approach based on formal scheduling analysis techniques and symbolic simulation. The tool supports heterogeneous architectures, complex task dependencies and context aware analysis. It determines system-level performance data such as end-to-end latencies, bus and processor utilisation, and worst-case scheduling scenarios. SymTA/S furthermore combines optimisation algorithms with system sensitivity analysis for rapid design space exploration. The paper gives an overview of current research interests in the SymTA/S project. - Author(s): J.J. Lee and V.J. Mooney
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 167 –182
- DOI: 10.1049/ip-cdt:20045078
- Type: Article
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167
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As multiprocessor system-on-a-chip (MPSoC) designs become more common, hardware/software codesign engineers face new challenges involving operating system integration. To speed up operating system/MPSoC codesign, the paper presents recent research in hardware/software partitioning of a real-time operating system (RTOS). After a brief overview of the δ hardware/software RTOS design framework, the authors focus on new results in deadlock detection and avoidance. Among various configured RTOS/MPSoC designs in this research, they show an example where a system with the deadlock detection hardware unit (DDU) achieves a 46% speed-up of application execution time over a system with deadlock detection in software. Similarly, they show another example where a system with the deadlock avoidance hardware unit (DAU) not only automatically avoids deadlock but also achieves a 44% speed-up of application execution time over a system avoiding deadlock in software; furthermore, in our example, the DAU only consumes 0.005% of the MPSoC total chip area. - Author(s): S. Künzli ; L. Thiele ; E. Zitzler
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 183 –192
- DOI: 10.1049/ip-cdt:20045081
- Type: Article
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Design space exploration is introduced as one of the major tasks in embedded system design. After reviewing existing exploration methods at various layers of abstraction, a generic approach is described based on multi-objective decision making, black-box optimisation and randomised search strategies. The interface between problem-specific and generic parts of the exploration framework is made explicit by defining an interface called PISA. This specification and implementation interface, and the availability of a wide range of randomised multi-objective search methods, makes the proposed framework accessible to a wide range of exploration problems. It resolves the problem that existing optimisation methods cannot be coupled easily to the problem-specific part of a design exploration tool. - Author(s): T.J. Todman ; G.A. Constantinides ; S.J.E. Wilton ; O. Mencer ; W. Luk ; P.Y.K. Cheung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 193 –207
- DOI: 10.1049/ip-cdt:20045086
- Type: Article
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Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. - Author(s): R. Leupers ; M. Hohenauer ; J. Ceng ; H. Scharwaechter ; H. Meyr ; G. Ascheid ; G. Braun
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 209 –223
- DOI: 10.1049/ip-cdt:20045075
- Type: Article
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p.
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Retargetable compilers can generate assembly code for a variety of different target processor architectures. Owing to their use in the design of application-specific embedded processors, they bridge the gap between the traditionally separate disciplines of compiler construction and electronic design automation. In particular, they assist in architecture exploration for tailoring processors towards a certain application domain. The paper reviews the state-of-the-art in retargetable compilers for embedded processors. Based on some essential compiler background, several representative retargetable compiler systems are discussed, while also outlining their use in iterative, profiling-based architecture exploration. The LISATek C compiler is presented as a detailed case study, and promising areas of future work are proposed. - Author(s): P. Marchal ; J.I. Gomez ; D. Atienza ; S. Mamagkakis ; F. Catthoor
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 224 –238
- DOI: 10.1049/ip-cdt:20045077
- Type: Article
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In recent years, the semiconductor industry has turned its focus towards heterogeneous multiprocessor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads into account and do not deal with the dynamic behaviour of these novel applications. The main limitations of current techniques are outlined and an approach for dealing with them is introduced. - Author(s): E.A. Lee and S. Neuendorffer
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 239 –250
- DOI: 10.1049/ip-cdt:20045065
- Type: Article
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The prevailing abstractions for software are better suited to the traditional problem of computation, namely transformation of data, than to the problems of embedded software. These abstractions have weak notions of concurrency and the passage of time, which are key elements of embedded software. Innovations such as nesC/TinyOS (developed for programming very small programmable sensor nodes called ‘motes’), Click (created to support the design of software-based network routers), Simulink with Real-Time Workshop (created for embedded control software) and Lustre/SCADE (created for safety-critical embedded software) offer abstractions that address some of these issues and differ significantly from the prevailing abstractions in software engineering. The paper surveys some of the abstractions that have been explored. - Author(s): W. Zhang ; Y.-F. Tsai ; M. Kandemir ; N. Vijaykrishnan ; M.J. Irwin ; V. De
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 251 –260
- DOI: 10.1049/ip-cdt:20045059
- Type: Article
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Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units. - Author(s): L. Benini and D. Bertozzi
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 261 –272
- DOI: 10.1049/ip-cdt:20045100
- Type: Article
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Performance and power of gigascale systems-on-chip (SoCs) is increasingly communication-dominated. Designers have to accommodate the communication needs of an increasing number of integrated cores while preserving overall system performance under tight power budgets. State-of-the-art SoC communication architectures start facing scalability as well as modularity limitations, and more advanced bus specifications are emerging to deal with these issues at the expense of silicon area and complexity. Communication architecture evolutions mainly regard bus protocols (to better exploit available bandwidth) and bus topologies (to increase bandwidth). In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a ‘revolutionary’ approach to provide a scalable, high performance and robust infrastructure for on-chip communication. The paper aims at surveying the evolution of the field, moving from SoC buses to forward-looking NoC research prototypes. The elements of continuity, as well as the key differences, will be captured, in an effort to extract general guiding principles in a fast-evolving domain. - Author(s): M. Amde ; T. Felicijan ; A. Efthymiou ; D. Edwards ; L. Lavagno
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 2, p. 273 –283
- DOI: 10.1049/ip-cdt:20045093
- Type: Article
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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.
Editorial: Embedded microelectronic systems: status and trends
Models of computation and languages for embedded system design
Analysis and optimisation of heterogeneous real-time embedded systems
System level performance analysis – the SymTA/S approach
Hardware/software partitioning of operating systems: focus on deadlock detection and avoidance
Modular design space exploration framework for embedded systems
Reconfigurable computing: architectures and design methods
Retargetable compilers and architecture exploration for embedded processors
Power aware data and memory management for dynamic applications
Concurrent models of computation for embedded software
Leakage-aware compilation for VLIW architectures
Network-on-chip architectures and design methods
Asynchronous on-chip networks
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