IEE Proceedings - Computers and Digital Techniques

Volume 151, Issue 2, March 2004

Volume 151, Issue 2

March 2004

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    • Simulation study of memory performance of SMP multiprocessors running a TPC-W workload
      Freshness specification for a class of asynchronous communication mechanisms
      Modelling economics of DFT and DFY: a profit perspective
      Residue-to-binary decoder for an enhanced moduli set
      LANG – algorithm for constructing unique input/output sequences in finite-state machines
      Energy-delay efficient filter cache hierarchy using pattern prediction scheme
      Multiplier architectures for GF(p) and GF(2n)
      Algorithm and architecture for a high density, low power scalar product macrocell

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