IEE Proceedings - Computers and Digital Techniques

Volume 150, Issue 5, September 2003

Volume 150, Issue 5

September 2003

Show / Hide details
    • Editorial: DATE03
      Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
      Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems
      Masking the energy behaviour of encryption algorithms
      Visualisation and resolution of encoding conflicts in asynchronous circuit design
      Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
      Schedulability analysis and optimisation for the synthesis of multi-cluster distributed embedded systems
      Development and application of design transformations in ForSyDe
      Behavioural specifications allocation to minimise bit level waste of functional units
      Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits
      Modelling and evaluation of substrate noise induced by interconnects
      Delay defect diagnosis based upon a statistical timing model – the first step
      Low-cost software-based self-testing of RISC processor cores

Most viewed content for this Journal


Most cited content for this Journal

We currently have no most cited data available for this content.

This is a required field
Please enter a valid email address