Home
>
Journals & magazines
>
IEE Proceedings - Computers and Digital Technique...
>
Volume 150
Issue 4
IEE Proceedings - Computers and Digital Techniques
Volume 150, Issue 4, July 2003
Volumes & issues:
Volume 150, Issue 4
July 2003
-
- Author(s): D. Kay and S. Mourad
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 189 –200
- DOI: 10.1049/ip-cdt:20030505
- Type: Article
- + Show details - Hide details
-
p.
189
–200
(12)
A methodology for test data compression and decompression in an interactive built-in self-test (iBIST) environment is presented. This methodology not only takes advantage of the strength of BIST in compression and test execution, but also overcomes BIST weaknesses by making it externally controllable. The data compression technique is realised in two steps. The first step consists of developing data to control the linear feedback self-register in generating patterns for random pattern resistant faults only. The second step uses a loss-less code to encode the control data and employs a loss-less and low-cost on-chip decodable coding scheme. A particular code was developed to illustrate the methodology; however, other codes may also be used within this environment. The proposed iBIST environment is well suited for compressing test data for the embedded logic cores in a system-on-a-chip. However, it can as well be used for component level testing. The experimental results obtained suggest that this compression scheme is comparable to the best technique available in the present literature. Furthermore, the decoding logic is estimated to be very low, e.g. less than 0.1% for cores of sizes of 100K gates or more. The architecture of test execution and its control including the decoding logic for the iBIST environment are also presented. The on- or off-chip first-in, first-out aspect of the architecture can ease the tight constraints of running a decoder synchronous to the external tester clock frequency. - Author(s): S.K. Lu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 201 –208
- DOI: 10.1049/ip-cdt:20030687
- Type: Article
- + Show details - Hide details
-
p.
201
–208
(8)
An efficient built-in self-repair approach, column-block-level reconfiguration methodology, is proposed. It is based on the concept of divided bit-line (DBL) for high-capacity memories including SRAMs and DRAMs, widely used in low-power memory designs. However, the inherent characteristics (two or more memory cells are combined together to divide the bit-line into several sub bit-lines) of divided bit-line memories have not been used for fault-tolerant applications. Therefore the column_block_repair (CBR) fault-tolerant architecture is proposed based on the structure of DBL for high-capacity memories. The redundant columns of a memory array are divided into column blocks and reconfiguration is performed at the column block level instead of the traditional column level. The fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DBL memories are also preserved. The reconfiguration mechanism of the CBR architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.58% and 0.012% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of the approach is compared with previous memory repair algorithms. It is found that the CBR approach improves the repair rate significantly. The yield improvement over traditional column-based approaches is also analysed. Simulated results show that the present approach can significantly improve fabrication yield. - Author(s): P. Rosinger ; B.M. Al-Hashimi ; N. Nicolici
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 209 –217
- DOI: 10.1049/ip-cdt:20030666
- Type: Article
- + Show details - Hide details
-
p.
209
–217
(9)
Mixed-mode BIST offers complete fault coverage with short test application times and small test data requirements. Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. Several techniques have been recently proposed for reducing power dissipation during BIST. The work presented addresses the problem of reducing power dissipation in mixed-mode BIST. A new mixed-mode test pattern generator is proposed with reduced power dissipation during test when compared with existing test pattern generators. This is achieved by combining the masking properties of AND/OR composition with LFSR reseeding. Extensive experiments were performed on several benchmark circuits using commercial synthesis and simulation tools to validate the efficiency and assess the overhead of the proposed solution. Experimental results show that reductions up to 20% in average power dissipation during test can be achieved when compared with traditional test pattern generators. - Author(s): L. Wang and A.E.A. Almaini
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 218 –226
- DOI: 10.1049/ip-cdt:20030575
- Type: Article
- + Show details - Hide details
-
p.
218
–226
(9)
Multilevel logic simplification plays a very important role to achieve high quality digital circuits in the design flow of application specific integrated circuit or a field programmable gate array products. The fundamental concept of unateness, is extended to the concept of containment for Boolean functions. Accordingly, the unate recursive paradigm, which is successfully employed in the two-level logic minimisation, is adapted to containment recursive paradigm for multilevel logic simplification of incompletely specified multiple output Boolean functions. Consequently, the functional ‘don't cares’ of Boolean functions can be extracted and utilised based on the functionality, instead of the structural information like satisfiability don't cares and observability don't cares. The efficient application of functional don't cares is developed with respect to variable order and splitting equation strategies based on containment recursive paradigm. Furthermore, the algorithm is generalised to multiple output functions using an encoding method. Experimental results show that the containment recursive paradigm is fundamental and effective for multilevel logic simplification. - Author(s): M. Lajolo ; C. Passerone ; L. Lavagno
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 227 –238
- DOI: 10.1049/ip-cdt:20030691
- Type: Article
- + Show details - Hide details
-
p.
227
–238
(12)
A system-level design approach that enforces a separation between system behaviour and architecture is presented. The system designer focuses first on system behaviour, then looks for a suitable architecture to implement it, and finally verifies the performance. Techniques and tools are described to accurately evaluate the performance of a system at different levels of abstraction. The evaluation must be done dynamically, in a simulation framework, to capture runtime interaction among tasks and with the environment model. Moreover, it should be fast enough to enable the exploration of several algorithmic and architectural solutions in the search for the best implementation. Tunable models, where the designer can trade accuracy for speed, are essential for this purpose. - Author(s): M. McLoone and J.V. McCanny
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 239 –244
- DOI: 10.1049/ip-cdt:20030499
- Type: Article
- + Show details - Hide details
-
p.
239
–244
(6)
A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modern communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions. - Author(s): E.-G. Jung ; B.-S. Choi ; D.-I. Lee ; Y.-G. Won
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 150, Issue 4, p. 245 –251
- DOI: 10.1049/ip-cdt:20030690
- Type: Article
- + Show details - Hide details
-
p.
245
–251
(7)
In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect and the difficulty of synchronisation caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for SoC design methodology. A new handshake protocol is proposed using the return-to-zero data encoding scheme for the implementation of a new high performance asynchronous bus. Simulation results reveal that the proposed handshake protocol increases the read throughput of the asynchronous bus by 30.5%, and decreases the read latency by 12.5%.
Interactive built-in self-test compression for testing a system-on-a-chip
Built-in self-repair techniques for embedded RAMs
Dual multiple-polynomial LFSR for low-power mixed-mode BIST
Multilevel logic simplification based on a containment recursive paradigm
Scalable techniques for system-level cosimulation and coestimation
Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography
Handshake protocol using return-to-zero data encoding for high performance asynchronous bus
Most viewed content for this Journal
Article
content/journals/ip-cdt
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.
