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Volume 148
Issue 4
IEE Proceedings - Computers and Digital Techniques
Volume 148, Issue 4-5, July–September 2001
Volumes & issues:
Volume 148, Issue 4
July–September 2001
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- Author(s): S. Lee ; S. Omachi ; H. Aso
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 141 –146
- DOI: 10.1049/ip-cdt:20010652
- Type: Article
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p.
141
–146
(6)
A VLSI architecture for flexible-size fractal image coding is proposed. The main features of this architecture are that it is capable of performing fractal image coding based on quadtree partitioning without the external memory for the fixed domain pool and uses only local data communication. Since large domain blocks consist of small domain blocks, the calculations of distortion for all kinds of domain block are performed using only the domain pool, which is extracted from the smallest range blocks of the neighbouring processors. This architecture has a fast comparison module which can compute the distortions between a range block and the eight isometric transformations of domain blocks by one full rotation around the centre. - Author(s): S. Chattopadhyay
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 147 –151
- DOI: 10.1049/ip-cdt:20010666
- Type: Article
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p.
147
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(5)
Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power demands exploration of alternative avenues that could lead to better designs, albeit at the higher cost of computation. The author explores the avenue of genetic algorithm for a holistic view for synthesis of finite state machine (FSM) targeting power reduction by incorporating both state assignment and sequential element selection. Exhaustive experimentation performed on a large suite of benchmarks has established the fact that this tool results in state encodings with on average 46.08% reduction in power requirement over NOVA, without any significant increase in the number of product terms. The effectiveness of judicious flipflop selection has been demonstrated by showing that the approach with all D-flipflops as the sequential element requires 33.78% more power than the approach with a choice of D and T flipflop types. Moreover, as compared to the technique presented in LPSA, the algorithm presented here requires 38.96% less power when using a mix of D and T flipflops. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the genetic algorithm in solving this particular NP-complete problem. Further, the inherent parallelism of genetic algorithm makes the proposed scheme ideal for solving the problem in a multiprocessor environment. - Author(s): O. Diessel and G. Milne
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 152 –162
- DOI: 10.1049/ip-cdt:20010579
- Type: Article
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p.
152
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Reconfigurable computers based on field programmable gate array technology allow applications to be realised directly in digital logic. The inherent concurrency of hardware distinguishes such computers from microprocessor-based machines in which the concurrency of the underlying hardware is fixed and abstracted from the programmer by the software model. However, reconfigurable logic provides us with the potential to exploit `real' concurrency. It is therefore interesting to know how to exploit this concurrency, how to model concurrent computations, and which languages allow this dynamic hardware to be programmed most effectively. The purpose of this work is to describe an FPGA compiler for the Circal process algebra. In so doing, the authors demonstrate that behavioural descriptions expressed in a process algebraic language can be readily and intuitively compiled to reconfigurable logic and that this contributes to the goal of discovering appropriate high-level languages for run-time recon-figuration. - Author(s): N. Nicolici and B.M. Al-Hashimi
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 163 –166
- DOI: 10.1049/ip-cdt:20010663
- Type: Article
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p.
163
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(4)
Recently a new test application strategy for minimising of power dissipation during test applications in full scan sequential circuits was proposed. This paper investigates its applicability to partial scan sequential circuits. It is shown that, when compared to full scan sequential circuits, partial scan not only reduces the test area overhead and test application time, but also reduces the power dissipation during test applications and the computational time required for low power testable design space exploration. - Author(s): C.-T.D. Lo ; W. Srisa-an ; J.M. Chang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 167 –175
- DOI: 10.1049/ip-cdt:20010597
- Type: Article
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p.
167
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(9)
For the past three decades, the buddy system has been the method of choice for memory allocation because of its speed and simplicity. However, the software realisation indicates that the buddy system incurs the overhead of internal fragmentation, external fragmentation, and memory traffic due to splitting and coalescing memory blocks. This paper presents a thorough analysis of the buddy system and its generalised extension, i.e. the generalised buddy system. All problems associating with the generalised buddy system will be extensively investigated. These problems include internal fragmentation, boundary and size blind spots that are the major causes for external fragmentation, and lastly splitting and coalescing overhead that can slow down the system performance. In 1996, Chang and Gehringer introduced the modified buddy system which eliminates two major drawbacks. First, it eliminates the splitting and coalescing overhead associated with the buddy system. Secondly, it also eliminates the internal fragmentation by using a new marking algorithm that only allocates a requested size. However, the severity of external fragmentation resulting from boundary and size blind spot remains to be studied. We propose an extension to the design that can solve existing issues. The extension also includes the first-fit algorithm into hardware domain. Two solutions that can solve the issues of size and boundary blind spots are also proposed. These solutions involve bit shifting to solve the boundary blind spot and the generalised buddy system to solve the size blind spot. We also present the simulation results of the proposed solutions. These results clearly indicate that both the shifting and the generalised buddy system yield minimal improvement over the modified buddy system. However, we believe that for some applications, these approaches enhance memory utilisation. - Author(s): W.J. Knottenbelt ; S. Zertal ; P.G. Harrison
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 148, Issue 4, p. 176 –187
- DOI: 10.1049/ip-cdt:20010664
- Type: Article
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p.
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A distributed lock manager (DLM) provides distributed applications with a convenient means of synchronising their accesses to shared resources. The authors present a performance study of three different implementation strategies for a DLM considering both the layout of the lock database (centralised or distributed) and the strategy used to assign lock masters (static or dynamic). For each implementation strategy, accurate analytical models of communication cost, resource utilisation and lock request response time are developed. The models highlight bottlenecks in the system and show clearly for what mixes of incoming lock request types it is best to use static or dynamic lock master positioning. The analytical formulae are validated against a detailed event-driven simulation which uses realistic hardware parameters. This validation reveals a good agreement between analytical and simulation results, particularly with respect to communication cost, node and CPU utilisation, system capacity and the response time trend.
VLSI architecture for quadtree-based fractal image coding
Low power state assignment and flipflop selection for finite state machine synthesis—a genetic algorithmic approach
Hardware compiler realising concurrent processes in reconfigurable logic
Minimising power dissipation in partial scan sequential circuits
Performance analyses on the generalised buddy system
Performance analysis of three implementation strategies for distributed lock management
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