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IEE Proceedings - Computers and Digital Techniques

Volume 146, Issue 6, November 1999

Volume 146, Issue 6

November 1999

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    • Compiler/hardware co-design for instruction boosting in ILP processors
      Automatic router for the pin grid array package
      PASE-scan design: A new full-scan structure to reduce test application time
      Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation
      ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions
      Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

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