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Volume 146
Issue 3
IEE Proceedings - Computers and Digital Techniques
Volume 146, Issue 3, May 1999
Volumes & issues:
Volume 146, Issue 3
May 1999
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- Author(s): J. H. Kim and N. H. Vaidya
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 125 –130
- DOI: 10.1049/ip-cdt:19990420
- Type: Article
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p.
125
–130
(6)
Checkpoint and rollback recovery is a technique used to minimise the loss of computation when failures occur. When a process rolls back and re-executes from the last checkpoint, the cost (loss) incurred by redoing the lost computation may be larger than that to execute the original computation. In addition to completion time delay, other performance metrics (e.g. user's satisfaction in real-time on online transaction applications) may also degrade by unexpected failure and recovery. The paper determines how redo overhead factor for unexpected execution overhead affects the performance of recovery scheme. It analyses the performance of three recoverable schemes (incorporating redo overhead factor): multiple fault-tolerant scheme using checkpointing and rollback recovery, single fault-tolerant scheme, and a two-level scheme. - Author(s): J. D. Huang ; J. Y. Jou ; W. -Z. Shen
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 131 –138
- DOI: 10.1049/ip-cdt:19990122
- Type: Article
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p.
131
–138
(8)
Roth-Karp decomposition is a classical functional decomposition technique; because it can decompose a node into a set of nodes with fewer numbers of fanins, it is one of the most popular techniques for look-up table (LUT)-based field-programmable gate array technology mapping. The compatible-class encoding problem in Roth-Karp decompositions discussed in the paper. It is shown how to formulate this problem as a symbolic-output encoding problem to exploit the feature of the two-output LUT architecture specifically. Based on this formulation an encoding algorithm is developed to minimise the number of LUTs used to implement the logic circuit. Experimental results show that the encoding algorithm can produce promising results to implement boolean networks in the logic synthesis environment for the two-output LUT architecture. - Author(s): B. Örencik
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 139 –150
- DOI: 10.1049/ip-cdt:19990533
- Type: Article
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p.
139
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(12)
The architecture of a hierarchical network suitable for interconnection of real-time client processes in a distributed multiprocessor environment is presented paper. A three-layer communication unit (CU) prototype is developed to offer the client processes communication services for real-time operation. The basic hardware of the CU consists of a PC compatible card connected at the VME bus. Client processes run on target cards (Motorola MVME-162) which are attached at the same bus. Target cards together with a CU form a node. Communication between nodes is handled by the CUs over an FDDI based hierarchical multiring structure. The network service layer (NSL), the lowest layer of the architecture, provides connectionless communication and routing services for the transport layer (TL) using a real-time `timed token protocol'. TL enables real—time end-to-end communication over established connections. The session layer (SL), the topmost layer of the protocol, provides to client processes location independent connection-oriented services and necessary support for migration. - Author(s): C. N. Zhang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 151 –159
- DOI: 10.1049/ip-cdt:19990217
- Type: Article
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p.
151
–159
(9)
Data security and fault tolerance are two important issues in modern communications. In most cases, they are studied and implemented separately. The author proposes an integrated approach for both fault tolerance and digital signature in the RSA implementation. It shares the same computations required by the Hash function, which is the major part of the digital signature and error detections and corrections. Therefore the total overheads are minimised. The proposed approach is able to detect and correct up to three errors occurring in the computation processes, including encryption, decryption and Hash function evaluation in the data transmission process. The principle of the proposed approach may also be used for other public key cryptography schemes. - Author(s): K. -W. Lam and S. -L. Hung
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 161 –167
- DOI: 10.1049/ip-cdt:19990190
- Type: Article
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p.
161
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The consistency of the database for concurrent transaction processing in database systems is guaranteed by concurrency control protocols which are normally implemented by two phase locking. Queuing network models are used to study two important locking protocols namely, the static and dynamic two phase locking protocols. Using simple combinatorial arguments and elementary probability theory, an efficient way of deriving expressions is provided for quantities such as the blocking delays of transactions, the probability of a lock being granted and the probability of deadlocks. Mean value analysis is then applied to the two models. The analysis is straightforward and the models are easy to understand. The analytic results show remarkable good agreement with simulation results. Some conclusions are drawn regarding the performance of locking protocols in the database systems. - Author(s): Y. Wan and C. L. Wey
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 3, p. 168 –172
- DOI: 10.1049/ip-cdt:19990530
- Type: Article
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p.
168
–172
(5)
The logarithm number system is an attractive alternative to the conventional number systems when data needs to be manipulated at a very high rate over a wide range. The major problem is deriving logarithms and antilogarithms quickly and accurately enough to allow conversions to and from conventional number representations. Efficient algorithms that convert the conventional number representation to binary logarithm representations are proposed. The algorithms adopt a factorisation approach to reduce the look-up table size and a nonlinear approximation method to reduce the computational complexity. Simulation results on IEEE single precision (24 bits) conversion are presented, and the conversion requires only one ROM table with 213×26 bits, one with 213×14 bits, and one with 213×5 bits, or a total of 360 kbits.
Analysis of failure recovery schemes for distributed shared-memory systems
Encoding in Roth-Karp decomposition with application to two-output LUT architecture
Design of BAĞ3 network architecture
Integrated approach for fault tolerance and digital signature in RSA
Analytic modelling of locking protocols in database systems
Efficient algorithms for binary logarithmic conversion and addition
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