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Volume 146
Issue 2
IEE Proceedings - Computers and Digital Techniques
Volume 146, Issue 2, March 1999
Volumes & issues:
Volume 146, Issue 2
March 1999
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- Author(s): B. A. Izadi ; F. Özgüner ; A. Acan
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 77 –82
- DOI: 10.1049/ip-cdt:19990181
- Type: Article
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p.
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A strongly fault-tolerant design for a d-dimensional hypercube multiprocessor is presented and its reconfigurability examined. The augmented hypercube has a spare node connected to each node of a subcube of dimension i, and the spare nodes are also connected as a (d−i)-dimensional hypercube. By utilising the circuit-switched capabilities of the communication modules of the spare nodes, a large number of faulty nodes and faulty links can be tolerated. Both theoretical and experimental results are presented. Compared with other proposed schemes the approach can tolerate significantly more faulty nodes and faulty links with a low overhead and no performance degradation. - Author(s): C. Yeh ; C. -C. Chang ; J. -S. Wang
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 83 –89
- DOI: 10.1049/ip-cdt:19990199
- Type: Article
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83
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Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several pieces of research. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern-oriented power modelling for improved technology mapping. We first perform a profitability study using the complete pattern to pattern transition data organised in tabular form. Then, we propose a probability-based, pattern-oriented technology mapping method. Empirical results on benchmark circuits demonstrate that the proposed method delivered an average of 13% power reduction compared with the traditional mapping method. - Author(s): B. K. Mohanty and P. K. Meher
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 91 –99
- DOI: 10.1049/ip-cdt:19990201
- Type: Article
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p.
91
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Systolic architectures are presented for bit-level VLSI implementation of 1D and 2D digital filters. The hardware utilisation in both our structures is 100%, and the throughput rate is 1 bit per clock period where the duration of a clock period is one full addition time. The structures have a very low latency of only three-cycle periods for the 1D FIR, four-cycle periods for 1D IIR and 2D FIR and five-cycle periods for the 2D IIR case. The structures are modular and regular. Apart from that, the input and output are in bit-serial order to have better compatibility with other dedicated systems. For high-throughput and low-latency implementation of the digital filters, we have proposed here a 2s complement a bit-level multiplier based on the Baugh–Wooley algorithm. - Author(s): S. -J. Wang and T. -M. Tsai
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 100 –106
- DOI: 10.1049/ip-cdt:19990532
- Type: Article
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p.
100
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Field programmable gate arrays (FPGAs) have been used in many areas of digital design. Because FPGAs are programmable, faults in them can be easily tolerated once fault sites are located. However, diagnosis of faults in FPGA has not yet been explored by researchers. A new methodology for the testing and diagnosis of faults in FPGAs is presented, based on built-in self-test. The proposed method imposes no hardware overhead, and requires minimal support from external test equipment. Test time depends only on the number of faults, and is independent of the chip size. With the help of this technique, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced. This method can also be used in fault-tolerant systems, in which a good functional circuit can still be mapped to a FPGA with faulty elements, as long as the fault sites are known. - Author(s): D. C. W. Pao ; S. P. Lam ; A. S. Fong
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 107 –113
- DOI: 10.1049/ip-cdt:19990096
- Type: Article
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p.
107
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Simulated annealing is an effective method for solving large combinatorial optimisation problems. Because of its iterative nature the annealing process requires substantial amount of computation time. A new parallel implementation based on the concurrency control theory of database systems is presented; the parallelised annealing process is serialisable. Concurrent updates to the base solution are allowed provided that they do not have data conflict. Using the travelling salesman problem as the example application, the parallel simulated annealing algorithm is implemented on a Motorola Delta 3000 shared-memory multiprocessor system with eight processors. With a moderate problem size of 400 cities, a speedup efficiency of over 90% is achieved at high annealing temperature and close to 100% at low annealing temperature. - Author(s): P. Williams and T. York
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 114 –118
- DOI: 10.1049/ip-cdt:19990123
- Type: Article
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114
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The hardware discussed in the paper employs field programmable logic devices to interface with memory components and, unlike previous implementations, utilises dynamic RAM without compromising performance. The network offers the opportunity to estimate process parameters without recourse to image reconstruction. Tests reveal speedups of 17, 22 and 6 for image reconstruction, void fraction estimation and flow regime classification, respectively, from electrical capacitance tomography data. - Author(s): N. Y. Lee
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 119 –121
- DOI: 10.1049/ip-cdt:19990200
- Type: Article
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In 1998, Shao proposed two new digital signature schemes which were claimed to be unbreakable if the factorisation and the discrete logarithms are simultaneously unsolvable. However, this paper shows that, if one has the ability to solve the factorisation problem, Shao's signature schemes can be broken. - Author(s): W. -H. He and T. -C. Wu
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 146, Issue 2, p. 123 –124
- DOI: 10.1049/ip-cdt:19990198
- Type: Article
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p.
123
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Petersen and Michels showed that Zheng's signcryption schemes lose confidentiality to gain nonrepudiation. They also proposed another signcryption scheme modified from a signature scheme giving message recovery. We show that the Petersen–Michels scheme still violates the unforgeability property, and propose an improvement that overcomes the security leak inherent in the Petersen–Michels scheme. Our improvement is as efficient as previous signcryption schemes with respect to both the computational cost and the communication overhead.
Highly fault-tolerant hypercube multicomputer
Power-driven technology mapping using pattern-oriented power modelling
High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters
Test and diagnosis of faulty logic blocks in FPGAs
Parallel implementation of simulated annealing using transaction processing
Hardware implementation of RAM-based neural networks for tomographic data processing
Security of Shao's signature schemes based on factoring and discrete logarithms
Cryptanalysis and improvement of Petersen–Michels signcryption scheme
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