IEE Proceedings - Computers and Digital Techniques

Volume 146, Issue 1, January 1999

Volume 146, Issue 1

January 1999

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    • Nondeterministic AND-EXOR minimisation by using rewrite rules and simulated annealing
      Self-checking synchronous controller design
      PTM: Technology mapper for pass-transistor logic
      Technology mapping for simultaneous gate and interconnect optimisation
      Performance evaluation of TCP/IP protocol implementations in end systems
      Haar spectra-based entropy approach to quasi-minimisation of FBDDs
      Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems
      Graph-based detailed router for hierarchical field-programmable gate arrays
      Fuzzy time point compatibility reasoning for microprocessor systems

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