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Volume 142
Issue 4
IEE Proceedings - Computers and Digital Techniques
Volume 142, Issue 4, July 1995
Volumes & issues:
Volume 142, Issue 4
July 1995
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- Author(s): L.A.M. Bennett
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 241 –248
- DOI: 10.1049/ip-cdt:19952016
- Type: Article
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p.
241
–248
(8)
Spectral operations are derived for the processing of multi-output binary logic functions. It is shown that these operations form the basis of a design method suitable for the synthesis of networks for realising such functions. The resulting networks are essentially cellular arrays with cells consisting of simple gate arrays and interconnections. The method contributes to a reduction in silicon area requirement by the use of short interconnections and by limiting each gate output load to unity thus allowing smaller transistors to be used. A worked example is included to demonstrate the application of the method. - Author(s): J.T. Proudfoot and S.M. Ngwira
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 249 –254
- DOI: 10.1049/ip-cdt:19951993
- Type: Article
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p.
249
–254
(6)
A method based on intersecting incompatible tuples is developed to determine the best disjunctive decomposition of complex logic functions, for use, primarily, with implementations on a cascaded memory structure, but also of use for other architectures. Classical decomposition theory is extended to allow the analysis of large input, multiple output functions which are specified only by their ON terms and include 'don't care' input values (i.e. modern PLA-style descriptions). An algorithm is presented together with implementation results which demonstrate an improvement in the size of function which may viably be searched exhaustively to find an overall optimum solution. - Author(s): K. Bilinski ; J.M. Saul ; E.L. Dagless
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 255 –262
- DOI: 10.1049/ip-cdt:19952017
- Type: Article
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p.
255
–262
(8)
A new algorithm for verifying the equivalence of parallel controller designs is presented along with its implementation. The controller is specified using a Petri net and its implementation is given as a netlist. The reachability graph of the Petri net is generated and simultaneously the network is implicitly simulated. By exploiting information from the reachability graph a reduction of the time and memory needed for verification has been achieved. Experimental results show that this approach is especially appropriate for parallel controller verification. - Author(s): T. Kozlowski ; E.L. Dagless ; J.M. Saul ; M. Adamski ; . Szajna
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 263 –271
- DOI: 10.1049/ip-cdt:19951886
- Type: Article
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p.
263
–271
(9)
A system for synthesising synchronous parallel controllers is presented. The system comprises a set of Petri net based CAD tools that have been added to an existing sequential synthesis system. Modules dedicated to the Petri net approach implement algorithms, which test the Petri net controller representation, provide an improved place encoding, and realise a novel method of generating state transition graphs from Petri nets. The algorithms are based on a new method of constructing a restricted reachability graph of a net. The system incorporates different design approaches, and so enables a designer to choose a solution that meets the specific needs of a design best. Benchmark comparisons between Petri net originated designs and equivalent FSMs show that the former are considerably more efficient in terms of area and speed when designing highly parallel circuits. - Author(s): W. Mao and C. Boyd
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 272 –278
- DOI: 10.1049/ip-cdt:19951991
- Type: Article
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p.
272
–278
(7)
Design of cryptographic protocols for authentication and key management is known to be a difficult problem. Although much research has been devoted to analysis techniques there remains a lack of basic design principles. In the paper a common method of protocol design is identified which contributes to protocol problems in a number of ways. This is the practice of encrypting all relevant fields using a reversible cryptographic transformation. A new design principle and a complementary notation are introduced which help protocol designers to identify what form of encryption is really required. Several examples are used to illustrate the problems and to show how the design principle and notation may be used in practice. - Author(s): A.E.A. Almaini ; J.F. Miller ; P. Thomson ; S. Billina
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 279 –286
- DOI: 10.1049/ip-cdt:19951885
- Type: Article
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p.
279
–286
(8)
The use of genetic algorithms for the generation of optimal state assignments for synchronous finite state machines (FSM) is proposed. Results are presented to show that, in all examples attempted, the resulting state assignments are better than or at least as good as those produced by SPECTRAL, NOVA and MUSTANG and also closed partition assignments. On average, the genetic algorithm produced assignments with 33% less logic than the best produced by other algorithms. - Author(s): W.-C. Wu ; C.-L. Lee ; J.-E. Chen ; W.-Y. Lin
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 287 –292
- DOI: 10.1049/ip-cdt:19951867
- Type: Article
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p.
287
–292
(6)
The paper investigates distributed fault simulation by pattern partitioning for sequential circuits. Simulation is done by making each distributed machine perform fault-free simulation with preceding patterns and then perform fault simulation with its own patterns. The fault simulation is accelerated since the number of patterns needed to be performed fault simulation for each machine is reduced by a factor of n, the number of machines, and the faults detected by any machine are dropped through communication of the network. A superlinear speedup can be obtained because this method can automatically remove the Case 1 faults, which are time consuming faults and would be considered to be undetected in the traditional three-valued fault simulation but are in fact truly detected. A mathematical model is also presented to predict the performance of the distributed fault simulation. - Author(s): P.-W. Shew ; P.-Y. Hsiao ; Y.-C. Lim
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 293 –298
- DOI: 10.1049/ip-cdt:19951988
- Type: Article
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p.
293
–298
(6)
The authors present a new algorithm for both two-layer and three-layer over-the-cell channel routing in the standard cell VLSI design. The approach exploits vacant terminals on the channel boundary effectively. It considers the following factors simultaneously to select net segments for routing over the cells: density distribution in the channel, the longest path in the vertical constraint graph, elimination of cycles in the vertical constraint graph and reduction in maximum cliques in the horizontal constraint graph. With respect to the PRIMARY 1 benchmark examples, the router achieved a 41.3% improvement over the Greedy channel router (one without using over-the-cell area) for a two-layer routing model and a 61.0% improvement for a three-layer routing model. This outperforms all previous algorithms. - Author(s): O.A. Petlin ; S.B. Furber ; A.M. Romankevich ; V.V. Groll
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 299 –305
- DOI: 10.1049/ip-cdt:19951982
- Type: Article
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p.
299
–305
(7)
A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach. - Author(s): G.I. Papadimitriou and D.G. Maritsas
- Source: IEE Proceedings - Computers and Digital Techniques, Volume 142, Issue 4, p. 306 –312
- DOI: 10.1049/ip-cdt:19951866
- Type: Article
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p.
306
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A learning automata based random access protocol for WDM passive star networks is introduced. The proposed protocol makes use of learning automata to achieve a high throughput and a low delay under any load conditions. An array of learning automata that determines the transmission probability of each wavelength is placed at each station. After each slot the transmission probability of each wavelength is modified according to the network feedback information. The asymptotic behaviour of the system which consists of the automata and the network is analysed and it is proved that under any load conditions, the transmission probability asymptotically tends to take its optimum value. Extensive simulation results are presented which indicate that the use of the proposed learning automata based scheme leads to a significant improvement of the network's performance.
Synthesis of multioutput logic networks using spectral techniques
Efficient method for the identification of optimum disjunctive decompositions of complex logic functions
Efficient functional verification algorithm for Petri-net-based parallel controller designs
Parallel controller synthesis using Petri nets
Methodical use of cryptographic transformations in authentication protocols
State assignment of finite state machines using a genetic algorithm
Distributed fault simulation for sequential circuits by pattern partitioning
Efficient height reduction over-the-cell channel router
Designing asynchronous sequential circuits for random pattern testability
Self-adaptive random-access protocols for WDM passive star networks
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