IEE Proceedings - Circuits, Devices and Systems
Volume 153, Issue 3, June 2006
Volumes & issues:
Volume 153, Issue 3
June 2006
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- Author(s): M. Ottavi ; S. Pontarelli ; V. Vankamamidi ; A. Salsano ; F. Lombardi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 199 –206
- DOI: 10.1049/ip-cds:20050094
- Type: Article
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p.
199
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The authors present a novel memory architecture for quantum-dot cellular automata (QCA). The proposed architecture combines the advantage of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory, hence its name is ‘hybrid’. This hybrid architecture utilises a novel arrangement in the addressing circuitry of the QCA loop for implementing the memory-in-motion paradigm. An evaluation of latency and area is pursued. It is shown that while for a serial memory, latency is O(N) (where N is the number of bits in a loop), a constant latency is accomplished in the hybrid memory. For area analysis, a novel characterisation that considers cells in the logic circuitry, interconnect in addition to the unused portion of the Cartesian plane (i.e. the whole geometric area encompassing the QCA layout), is proposed. This is referred to as the effective area. Different layouts of the hybrid memory are proposed to substantiate the reduction in effective area. - Author(s): M. Dubois ; Y. Savaria ; D. Haccoun ; N. Bélanger
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 207 –213
- DOI: 10.1049/ip-cds:20045113
- Type: Article
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p.
207
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Novel methods for implementing low-power hardware and configurable architectures comprising several different kinds of shift registers in field programmable gate arrays are presented. New approaches are also described to reduce the power dissipation of shift register structures without compromising their configurability. The proposed structures are particularly effective to reduce the power dissipation of shift registers of medium and large lengths. A systematic method to select the best shift register structure is also provided. The proposed structures and the selection method are generic, and they can be configured statically or dynamically. It is shown that they are well suited for implementing powerful convolutional encoders and suitable decoders associated with forward error correction techniques such as iterative threshold decoding. - Author(s): A.Ü. Keskin and D. Biolek
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 214 –218
- DOI: 10.1049/ip-cds:20050304
- Type: Article
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214
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A CDTA-based quadrature oscillator circuit is proposed. The circuit employs two current-mode allpass sections in a loop, and provides high-frequency sinusoidal oscillations in quadrature at high impedance output terminals of the CDTAs. The circuit has no floating capacitors, which is advantageous from the integrated circuit manufacturing point of view. Moreover, the oscillation frequency of this configuration can be made adjustable by using voltage controlled elements (MOSFETs), since the resistors in the circuit are either grounded or virtually grounded. - Author(s): F. Yuan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 219 –230
- DOI: 10.1049/ip-cds:20045058
- Type: Article
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219
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The author presents an in-depth study of the topologies and characteristics of low-voltage CMOS current amplifiers. The input impedance, output impedance, bandwidth, noise performance, and dynamic range of current amplifiers are investigated both analytically and numerically. Several new circuit techniques specific to low-voltage CMOS current-mode circuits including pseudo-cascode, current–current feedback, inductive series peaking, and joint resistive/inductive series peaking and current–current feedback for bandwidth enhancement, output impedance boosting, and dynamic range improvement are proposed. To provide a quantitative comparison and to quantify the effect of these new circuit techniques, the current amplifiers investigated are implemented in TSMC 0.18 μm 1.8 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM3V3 device models that count for both device parasitics and high-order effects. Simulation results are compared with those from analytical analysis. - Author(s): D. Piombo and R. Zunino
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 231 –240
- DOI: 10.1049/ip-cds:20050105
- Type: Article
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p.
231
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Soft-max (SM) operation in vector signal processing usually serves to remap an input distribution within a predetermined range; by a scalar (gain) parameter one can adjust the sharpness of the overall process. Thus, to exhibit practical interest, design approaches to SM circuitry should be consistent and, at the same time, allow dynamic gain control. Therefore, a preliminary analysis applies a power-series expansion to soft-max processing and derives both an analytical upper bound to the resulting approximation error, and a convenient mathematical approach to gain control. Theoretical achievements drive the subsequent current-mode circuit design, which yields a modular architecture that enhances overall parallelism. For simplicity, a digital mechanism supports the dynamic gain control in soft-max processing, but analogue solutions are also feasible. Simulation results in both static and dynamic tests confirmed the accuracy and effectiveness of the proposed design method. The cell-based circuit architecture sharply reduces VLSI complexity and limits power consumption. - Author(s): C.-M. Lee and I-K. Fong
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 241 –246
- DOI: 10.1049/ip-cds:20045104
- Type: Article
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p.
241
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The robust H∞ filtering problem subject to pole-placement constraints for continuous-time systems with the polytopic type uncertainties is considered. Different from those considered in the literature, the regional pole-placement constraints considered here focus on the filter dynamics. To solve the problem, the π-sharing theory is extended to offer a stability criterion that covers the bounded real lemma as a special case, and the linear matrix inequality approach is adopted to develop filter design methods based on the convex optimisation procedure. One numerical example is given to illustrate the proposed methods. - Author(s): C.-H. Kuo ; S.-L. Chen ; S.-I. Liu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 247 –252
- DOI: 10.1049/ip-cds:20045168
- Type: Article
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p.
247
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A high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5 μm CMOS DPDM process. With a clock rate of 16.6 kHz, the power consumption is 42.5 mW under 5 V supply voltage. The equivalent resolution less than 16 μT can be achieved within the range of ±10 mT. After off-line calibration, the remaining offset is 0.017 mT and its gain error is smaller than 0.4%. - Author(s): M.-W. Phyu ; W.-L. Goh ; K.-S. Yeo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 253 –260
- DOI: 10.1049/ip-cds:20050163
- Type: Article
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p.
253
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Latches and flip-flops play important roles in the building of digital CMOS circuits. In the paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic pulse generator are proposed. The pulse generator is then used with the proposed latch to create a low-power and high-performance single edge-triggered flip-flop (SETFF). The proposed positive level-sensitive latch deploys two non-precharge (static) n-stages (SN) in a true-single-phase-clocking (TSPC) scheme. We therefore named our latch SN2. This is because the TSPC latches have the advantage of single clock distribution, less clock routing area, high-speed and no clock skew. Based on the 0.18-μm single-poly six-metal CMOS technology, the SPECTRE simulation results derived for typical input activities showed that the latch can attain a maximum power saving of 29.1% when compared to other reported designs. As for our proposed flip-flop that is derived from the proposed SN2 latch with incorporation of a dynamic pulse generator circuit, it is able to outperform other reported works by about 16.2% to 67.4% for its power-delay product (PDPCQ) that is taken with respect to the clock-to-output delay. The two new designs are therefore suitable for used in low-power and high-performance CMOS VLSI/ULSI applications. - Author(s): Z. Li and C. Chen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 261 –267
- DOI: 10.1049/ip-cds:20045165
- Type: Article
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p.
261
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A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures. - Author(s): A. Dei and M. Valle
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 269 –273
- DOI: 10.1049/ip-cds:20045088
- Type: Article
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p.
269
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Charge injection in MOS switches in a deep submicron technology has been analysed. The analysis has been extended to the general case of including the conduction of the MOS transistor in the moderate and weak inversion regions, using a continuous and physical formulation based on the EKV model. SPICE simulations, based on the BSIM3v3 model, which ensures the charge conservation, have demonstrated the validity of our work. - Author(s): L. Zhang ; R. Raut ; Y. Jiang ; U. Kleine
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 274 –280
- DOI: 10.1049/ip-cds:20045126
- Type: Article
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p.
274
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The shortcomings of conventional separate placement and global routing becomes more prevalent for analogue integrated circuits that often involve complex constraints. The paper presents a novel two-stage placement technique to solve the analogue macro-cell placement problem. The entire placement procedure is divided into global placement and detailed placement. During the global placement, a hybrid genetic placement approach using a half-perimeter net-length estimator is employed. It performs a rough and quick search to locate the region of the optimum. In the detailed placement, a very fast simulated re-annealing placement approach and a minimum-Steiner-tree-based global routing are performed simultaneously. In this way, the optimum can be found by searching a relatively small region. The experiments show this promising algorithm, which provides the satisfactory results comparable to expert manual placements, can help generate higher quality layouts than conventional approaches. - Author(s): N. Stojadinović ; I. Manić ; V. Davidović ; D. Danković ; S. Djorić-Veljković ; S. Golubović ; S. Dimitrijev
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 3, p. 281 –288
- DOI: 10.1049/ip-cds:20050050
- Type: Article
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p.
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The effects of DC gate bias stressing on threshold voltage and channel carrier mobility in commercial power VDMOSFETs from two different manufacturers are studied. Underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. Apart from certain quantitative differences, it is shown that gate bias stressing has qualitatively the same effects and causes significant threshold voltage shift and mobility degradation in both VDMOS devices. Negative gate bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger after stressing by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon ≡Si•o defects into the oxide conduction band and subsequent hole tunnelling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis–H are proposed to be the main mechanisms responsible for build-up of positive oxide-trapped charge and interface traps, respectively. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects ≡Sio••Sio≡ is shown to be responsible for build-up of oxide-trapped charge, and subsequent electro-chemical reactions of interfacial precursors ≡Sis–H with charged oxide traps ≡Sio+•Sio≡ and H+ ions for that of interface traps.
QCA memory with parallel read/serial write: design and analysis
Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders
Current mode quadrature oscillator using current differencing transconductance amplifiers (CDTA)
Low-voltage CMOS current-mode circuits: topology and characteristics
Soft-max circuit design with adjustable gain
Robust H∞ filter design with filter pole constraints via π-sharing theory
Magnetic-field-to-digital converter using PWM and TDC techniques
Low-power/high-performance explicit-pulsed flip-flop using static latch and dynamic pulse generator
A low-power low-noise CMOS analogue multiplier
Modelling charge injection in MOS analogue switches using a compact model in a deep submicron technology
Two-stage placement for VLSI analogue layout designs
Electrical stressing effects in commercial power VDMOSFETs
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