IEE Proceedings - Circuits, Devices and Systems
Volume 152, Issue 5, October 2005
Volumes & issues:
Volume 152, Issue 5
October 2005
-
- Author(s): R.L. Moreno and E.C. Rodrigues
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 401 –406
- DOI: 10.1049/ip-cds:20045132
- Type: Article
- + Show details - Hide details
-
p.
401
–406
(6)
A low-noise amplifier (LNA) fabricated in a standard 0.35 μm AMS CMOS process is described. The LNA is part of a telemetry system which is part of a R&D project for biomedical applications. The goal is to build a low-power 174–230 MHz RF transmitter–receiver suitable for measuring blood pressure on a patient body. The low noise amplifier is composed of transistors only, which allows full integration on a standard CMOS process. The LNA has been measured to have a noise figure of 2.6 dB and a 21.7 dB gain at 200 MHz. The input IP3 is −12 dBm. - Author(s): C.W. Yang ; Y.K. Fang ; S.F. Chen ; C.S. Lin ; C.Y. Lin ; W.D. Wang ; T.H. Chou ; P.J. Lin ; M.F. Wang ; T.H. Hou ; L.G. Yao ; S.C. Chen ; M.S. Liang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 407 –410
- DOI: 10.1049/ip-cds:20041216
- Type: Article
- + Show details - Hide details
-
p.
407
–410
(4)
A novel technique is proposed for forming high-K dielectric of HfSiON by sequentially doping base oxide with Hf and nitridation with NH3. The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared to conventional SiO2 gate dielectric at the same equivalent oxide thickness (EOT). Additionally, negligible flatband voltage shift is achieved with this technique. Excellent performances in electrical stressing are also demonstrated by the dielectric. - Author(s): A. Tajalli ; M. Atarodi ; H. Bazargan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 411 –416
- DOI: 10.1049/ip-cds:20045151
- Type: Article
- + Show details - Hide details
-
p.
411
–416
(6)
This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU). - Author(s): S.O. Cannizzaro ; G. Palumbo ; S. Pennisi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 417 –424
- DOI: 10.1049/ip-cds:20045057
- Type: Article
- + Show details - Hide details
-
p.
417
–424
(8)
A simple and comprehensive study of the high-frequency harmonic distortion of two-stage Miller-compensated CMOS OTAs used in inverting configuration is presented. An improved extension of a symbolic approach recently proposed by the authors is adopted here. As a result of a better formalisation, inaccuracies incurred by the original formulation can be avoided and closed-form expressions of second- and third-order harmonic distortion factors are derived, whose precision extends well beyond the amplifier's gain-bandwidth product. The correctness of both this approach and the expressions derived was confirmed by comparison with computer simulations at transistor level. - Author(s): V.J. Vijayakrishna ; S. Vaishnav ; N. DasGupta ; A. DasGupta
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 425 –432
- DOI: 10.1049/ip-cds:20045087
- Type: Article
- + Show details - Hide details
-
p.
425
–432
(8)
A unified model for the I–V characteristics of HEMTs valid for the subthreshold, linear and saturation regions of operation is presented. There is a smooth transition in the current from subthreshold to above threshold and also from linear to saturation. This results in highly continuous channel conductance (gds) and transconductance (gm), which are important circuit parameters in small signal analysis. Comparisons with experimental data show that the model is accurate and valid over a wide range. Further, it is established that the model holds good promise for analogue circuit design by subjecting it to a few benchmark tests. In addition, the model, which was originally developed for n-channel HEMTs, has been suitably modified to predict the I–V characteristics of p-channel HEMTs as well. Finally, an inverter circuit using p-channel HEMT as load and n-channel HEMT as driver has been successfully simulated using the circuit simulator SABER and the nature of the inverter characteristics are found to agree well with the experimental results. - Author(s): A. Kabbani ; A. Kabbani ; D. AlKhalili ; A.J. Al-Khalili
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 433 –440
- DOI: 10.1049/ip-cds:20041016
- Type: Article
- + Show details - Hide details
-
p.
433
–440
(8)
A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented. This model does not depend on extracted or fitting parameters. Instead it depends on device model parameters, and hence becomes portable across technology generations. Delay analytical model verification was performed against Spectre simulations using a BSIM3v3 model for a wide range of device sizes, capacitive loads and transition times. Model portability was tested across three DSM technologies: UMC's 0.13 μm and TSMC's 0.18 μm and 0.25 μm. The model exhibits high accuracy with average and maximum errors of about 2.3% and 10% compared to simulation. - Author(s): D. Dousset ; A. Issaoun ; F.M. Ghannouchi ; A.B. Kouki
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 441 –450
- DOI: 10.1049/ip-cds:20045077
- Type: Article
- + Show details - Hide details
-
p.
441
–450
(10)
An accurate, robust and broadband method for the direct extraction of heterojunction bipolar transistor (HBT) small-signal model parameters is proposed. This new approach, modified from previous work by the authors, including additional equivalent-circuit elements, go and Cce, can be applied accurately to all transistor bias points covering the entire forward bias region. First, hot and cold bias conditions are used to determine the parasitic elements (Lb, Lc, Le, Cbep, Ccep and Cbcp), then the access resistances (Rb, Rc, RE) are determined using DC flyback measurement. Finally, the intrinsic elements are extracted analytically through a judicious and rigorous derivation of closed-form expressions of the Z-parameters deduced from the measured S-parameters. The analytical expressions allow us to obtain a unique physical solution without having to use a nonlinear system. The method is applied at multiple bias points and over a wide range of signal frequencies. As the physical solution is unique, all the circuit elements are determined without any optimisation or any knowledge of the geometrical or process parameters of the device. To assess the effectiveness of the present method three HBT devices, with 2×25 μm2, 2×20 μm2 and 2×10 μm2 emitter areas from two different foundries, are studied. Excellent agreement is obtained between the model and measurements up to 20 GHz and for all amplifier bias classes. - Author(s): L.H.C. Ferreira ; T.C. Pimenta ; R.L. Moreno
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 451 –455
- DOI: 10.1049/ip-cds:20045099
- Type: Article
- + Show details - Hide details
-
p.
451
–455
(5)
The authors describe the silicon implementation of a new sample-and-hold circuit topology. Its main feature is the self correction of the offset voltage that is generated mainly by the mismatch on the differential pair at the input and the charge injected by the NMOS switches in the sampling capacitor. The circuit was implemented in a CMOS CYE 0.8 μm n-well process from AMS. The results, initially obtained from simulations, were compared to real laboratory measurements. The comparison indicates that the measurements and the simulated results have a very strong correspondence. The real circuit is capable of reducing the total sample-and-hold output error to just 0.14% at a sampling rate of 250 kHz, so that a system which operates at 250 K samples can be implemented. - Author(s): R.G. Carvajal ; J. Galan ; A. Torralba ; F. Muñoz ; J. Ramirez-Angulo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 456 –464
- DOI: 10.1049/ip-cds:20045092
- Type: Article
- + Show details - Hide details
-
p.
456
–464
(9)
A gm-C bandpass biquad filter featuring two decades of centre frequency tuning capability and a wide range of quality factor tunability is presented. It uses a new linear operational transconductance amplifier (OTA) based on two crosscoupled class-AB pseudo-differential pairs, which exhibits a wide transconductance adjustability range with low power consumption. The filter has been fabricated in a standard 0.8 μm CMOS process. Experimental results show a frequency tuning range from 300 kHz to 32 MHz and a maximum quality factor of 501. The filter is operated at 2 V supply voltage with a power consumption ranging from 1.18 to 1.8 mW. - Author(s): J. Bayard
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 465 –469
- DOI: 10.1049/ip-cds:20045014
- Type: Article
- + Show details - Hide details
-
p.
465
–469
(5)
A method for making a sinusoidal frequency tripler, whatever the input signal frequency value, is presented. The theoretical study relates mainly the minimisation of the 5th and 7th harmonics in the output signal. SPICE simulations and measurements on a prototype confirm the theoretical analysis. - Author(s): B. Bornoosh ; A. Afzali-Kusha ; R. Dehghani ; M. Mehrara ; S.M. Atarodi ; M. Nourani
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 471 –477
- DOI: 10.1049/ip-cds:20045179
- Type: Article
- + Show details - Hide details
-
p.
471
–477
(7)
A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two sub-blocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full scale (0.7 FS) with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25 μm CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 1.5 V. - Author(s): M. McLoone
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 478 –484
- DOI: 10.1049/ip-cds:20059027
- Type: Article
- + Show details - Hide details
-
p.
478
–484
(7)
A hardware performance analysis of the SHACAL-2 encryption algorithm is presented. SHACAL-2 was one of four private-key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative. To the author's knowledge, there has been no previous published research work conducted on hardware SHACAL-2 architectures. Consequently, in this paper, both iterative and pipelined designs are developed and implemented. A fully pipelined encryption SHACAL-2 architecture implemented on a Virtex-II XC2V4000 device achieves a throughput of over 25 Gbit/s. This is one of the fastest encryption algorithm implementations currently available. The iterative encryption architecture operates at 432 Mbit/s on the XC2V500 device. A comparison is provided between SHACAL-2 hardware designs that incorporate carry save adders and designs that include typical full adders. The SHACAL-2 decryption algorithm is also clearly defined in the paper as it was not provided in the NESSIE submission. - Author(s): C.H. Kao ; C.C. Tseng ; C.S. Hsieh
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 485 –487
- DOI: 10.1049/ip-cds:20045110
- Type: Article
- + Show details - Hide details
-
p.
485
–487
(3)
The paper presents a low-voltage (≤1 V) exponential function converter and its application to a current mode dB linear variable gain amplifier. The circuit is designed using MOS weak inversion translinear circuits and it is compact and power-efficient. Simulation results demonstrate the effectiveness of the proposed circuit.
CMOS LNA for wireless biomedical telemetry
Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application
Duty-cycle controller for low-jitter frequency-doubling DLL
Accurate estimation of high-frequency harmonic distortion in two-stage Miller OTAs
Unified analytical model of HEMTs for analogue and digital applications
Technology portable analytical model for DSM CMOS inverter delay estimation
Wideband closed-form expressions for direct extraction of HBT small-signal parameters for all amplifier bias classes
CMOS implementation of precise sample-and-hold circuit with self-correction of the offset voltage
1.33 mW, 2 V CMOS continuous-time bandpass filter with two decades of centre frequency tuning range and high Q
Proposal to lower the 5th and 7th harmonics in an aperiodic sinusoidal frequency tripler
Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications
Hardware performance analysis of the SHACAL-2 encryption algorithm
Low-voltage exponential function converter
-
- Author(s): N.R. Das ; P.K. Basu ; M.J. Deen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 488 –490
- DOI: 10.1049/ip-cds:20059073
- Type: Article
- + Show details - Hide details
-
p.
488
–490
(3)
- Author(s): L. Fu ; P. Lever ; H.H. Tan ; C. Jagadish ; P. Reece ; M. Gal
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 491 –496
- DOI: 10.1049/ip-cds:20045053
- Type: Article
- + Show details - Hide details
-
p.
491
–496
(6)
Two of the most important intermixing techniques, ion implantation and impurity free vacancy disordering, are investigated and compared in InGaAs/(Al)GaAs quantum well (QW) and quantum dot (QD) structures. For ion implantation induced intermixing, arsenic implantation was performed and the amount of interdiffusion created was found to vary as a function of implantation dose and temperature. Impurity free vacancy disordering was also enhanced by deposition of SiO2 in both QW and QD structures and annealing at different temperatures. In order to obtain large differential energy shifts for device integration using both methods, the essential issue of suppression of thermal interdiffusion using a TiO2 capping layer was also addressed. - Author(s): S. Banerjee ; K.A. Shore ; C.J. Mitchell ; J.L. Sly ; M. Missous
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 497 –501
- DOI: 10.1049/ip-cds:20045042
- Type: Article
- + Show details - Hide details
-
p.
497
–501
(5)
Growth of electroluminescent devices based on strain–compensated InxGa1−xAs/InyAl1−yAs has been undertaken. The very high conduction band offset of the strained material allows the design of such devices with very short emission wavelength. Device design and material characterisation for 2 μm emission has been undertaken. An analysis of the direct current amplitude modulation response of the strained structure is also performed. Strong room temperature emission with peaks around 1.55 μm dependent upon driving current has been observed under continuous wave reverse operational bias. This reverse bias emission was observed owing to the presence of interface states. Moreover experimentally measured current-voltage characteristics in forward bias are found to be in good agreement with theoretical predictions. - Author(s): A. Jiménez-P ; F.J. De la Hidalga-W ; M.J. Deen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 502 –508
- DOI: 10.1049/ip-cds:20045047
- Type: Article
- + Show details - Hide details
-
p.
502
–508
(7)
Despite the inappropriateness of the depletion approximation when the source-substrate junction is slightly forward biased, conventional SPICE models are being used to simulate digital integrated circuits implemented with dynamic threshold voltage MOSFETs (DTMOS). Based on PISCES simulations and experimental data, the correct modelling of DTMOS is discussed in this work. It is found that the dependence of the threshold voltage on the source-substrate forward bias can differ importantly from the conventional model at voltages above ∼0.4 V for long channel technologies, but it could agree with conventional models for voltages as high as ∼0.5 V for deep submicron technologies. This is explained in terms of the difference in substrate doping levels between such technologies, which is at least one order of magnitude. Mobility and transverse electric field always improve in the dynamic operation. However, the conventional models used by SPICE to calculate these two parameters, which are based on the depletion approximation, lead to important miscalculations. This is proven using the PISCES numerical solution of the Poisson equation considering the presence of mobile charge in the depletion region. With these results, some guidelines for the correct modelling of this device are generated. - Author(s): M.J. Deen ; R. Murji ; A. Fakhr ; N. Jafferali ; W.L. Ngan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 509 –522
- DOI: 10.1049/ip-cds:20045069
- Type: Article
- + Show details - Hide details
-
p.
509
–522
(14)
This paper presents results for a mixer, two voltage-controlled oscillators (VCOs) and a frequency doubler (FD) suitable for low-power CMOS radio frequency (RF) systems. Results are first described for a mixer which uses the body terminal of the transistor as one of the inputs to down-convert a 1.9 GHz RF signal to a 250 MHz intermediate-frequency signal. Next, two VCOs are described. The first VCO is an ultra-low-power oscillator designed to operate in the 2.4 GHz industrial scientific medical band with a supply of 0.4 V. The second VCO described is a fully integrated LC-tank VCO with automatic amplitude control operating at 4 GHz. Frequency tuning for this VCO is performed by accessing the body of cross-coupled transistors of the VCO core. Finally, a wideband, low-power implementation of a frequency doubler is presented. The frequency doubler consists of two identical unbalanced source-coupled pairs with different W/L ratios, whose inputs are connected in parallel and its output taken single-ended. The FD is based on the MOS transistor in saturation. All circuits were designed in a deep n-well 0.18 μm technology, allowing application of different potentials to the body of different NMOS transistors. - Author(s): I. Banerjee ; M. Morse ; J.-M. Verdiell ; D. Docter
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 523 –526
- DOI: 10.1049/ip-cds:20045049
- Type: Article
- + Show details - Hide details
-
p.
523
–526
(4)
From the time in 1965 when ‘Moore's Law’ – doubling of circuit density every 18 months approximately was predicted, scaling of transistors has progressed in accordance with the law. This was primarily enabled by technological advances in manufacturing equipment that allowed the ‘printing’ and manufacturing of smaller circuits. Occasionally, in-between, a new material was introduced in the manufacture of the circuits. However, from the 180 nm technology, new materials have been needed in every generation. As the circuit features get smaller, the necessity of new materials required becomes more apparent. The importance of these materials in the manufacturing of semiconductor devices will be illustrated in this paper along with some results. - Author(s): V.S.C. Manga Rao and S. Dutta Gupta
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 527 –531
- DOI: 10.1049/ip-cds:20045044
- Type: Article
- + Show details - Hide details
-
p.
527
–531
(5)
Pulse propagation through 1-dimensional stratified media is studied. The general features of pulse propagation in relation to the delay or advancement of the pulse are discussed. It is shown that in a lossless system with spatial symmetry the reflected and the transmitted pulses have the same delay or advancement. The phase times and the explicit output pulse profiles for an input Gaussian pulse are calculated. While recalling recent results for a variety of systems (resonant absorbers or heterogeneous medium in a Fabry-Perot cavity, a slab of negative index medium, a left-handed/right-handed periodic structure, etc.), new results involving coupled waveguides and a high finesse cavity containing an electromagnetically induced transparency (EIT) medium are presented. Calculations clearly show that for pulses with a carrier tuned at the resonance of the stratified media, one generally has subluminal propagation. Alternatively, in stop gaps or away from the resonances one ends up with superluminal transit. In the case of the EIT cavity it is shown that the large dispersion offered by the intracavity medium can lead to substantial superluminality (ng≃−106) with peak transmission as high as 20%. This is in sharp contrast to large signal attenuation for usual superluminal transit. Note also that EIT, to the best of the authors knowledge, has so far been used to achieve only slow light. - Author(s): B.M.A. Rahman ; T. Wongcharoen ; C. Themistos ; R. Abdallah ; A.K.M.S. Kabir ; E.O. Ladele ; N. Somasiri ; M.S. Alam ; M. Rajarajan ; K.T.V. Grattan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 532 –538
- DOI: 10.1049/ip-cds:20045052
- Type: Article
- + Show details - Hide details
-
p.
532
–538
(7)
A review of the characterisation of optical guided-wave devices using modal solutions, junction analysis and the beam propagation method, based on the numerically efficient finite element method, is presented. Numerically simulated results for mode propagation in optical waveguides and the characterisation of various photonic devices, such as photonic crystal fibres, semiconductor optical amplifiers, spot-size converters, power splitters and single polarisation waveguides, are presented. - Author(s): S.R. Das
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 539 –546
- DOI: 10.1049/ip-cds:20045050
- Type: Article
- + Show details - Hide details
-
p.
539
–546
(8)
One obvious way to significantly improve the testability of evolving embedded cores-based system-on-a-chip (SoC) and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself. This technique generates test patterns and evaluates test responses inside the chip system. The technique has been widely used in commercial VLSI products with appreciable success. The general methodology of BIST in the particular context of today's cores-based SoC technology is presented. - Author(s): Y. Ni
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 547 –555
- DOI: 10.1049/ip-cds:20045055
- Type: Article
- + Show details - Hide details
-
p.
547
–555
(9)
An electronic retina is a combination between image sensing and in situ signal processing on the same silicon chip. This smart image sensing and processing, realisable in common CMOS technology, is a valuable technique in real-time vision systems. In order to optimise the global performance of a vision machine where different levels of processing are implicated, this technique cannot be considered simply and only as an (intelligent) image sensor design problem. The local on-sensor information processing in an electronic retina should be placed in a more general context including algorithms, architectures and applications. This paper aims to give an overview of electronic retina-based vision systems and especially on the role that an electronic retina can play in real-time vision systems via some real examples from recent work. - Author(s): S.S. Ray ; S. Bandyopadhyay ; P. Mitra ; S.K. Pal
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 152, Issue 5, p. 556 –564
- DOI: 10.1049/ip-cds:20045051
- Type: Article
- + Show details - Hide details
-
p.
556
–564
(9)
Different bioinformatics tasks like gene sequence analysis, gene finding, protein structure prediction and analysis, gene expression with microarray analysis and gene regulatory network analysis are described along with some classical approaches. The relevance of intelligent systems and neural networks to these problems is mentioned. Different neural network based algorithms to address the aforesaid tasks are then presented. Finally some limitations of the current research activity are provided. An extensive bibliography is included.
Editorial: Computers and Devices for Communication (CODEC 04)
Study of intermixing in InGaAs/(Al)GaAs quantum well and quantum dot structures for optoelectronic/photonic integration
Current-voltage and light-current characteristics in highly strained InGaAs/InAlAs quantum cascade laser structures
Modelling of the dynamic threshold MOSFET
Low-power CMOS integrated circuits for radio frequency applications
Materials in semiconductor processing for high speed circuits: from electrical to optical circuits
Sub and superluminal propagation through stratified media
Finite element characterisation of photonic devices for optical communications
Self-testing of cores-based embedded systems with built-in hardware
Smart image sensing in CMOS technology
Bioinformatics in neurocomputing framework
Most viewed content for this Journal
Article
content/journals/ip-cds
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.