IEE Proceedings - Circuits, Devices and Systems
Volume 151, Issue 5, October 2004
Volumes & issues:
Volume 151, Issue 5
October 2004
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- Author(s): N. Tilston ; A.D. McLachlan ; A.J. Sangster
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 385 –394
- DOI: 10.1049/ip-cds:20040344
- Type: Article
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p.
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In airborne military phased array radar systems, detection capability is influenced as much by receiver linearity as it is by system noise performance. The extremely wide dynamic range of the target returns in such systems leads to challenging receiver design compromises between amplifiers exhibiting low distortion or low thermal noise. Conventional methods that are used to improve linearity, such as increasing device size, bias current or supply voltage, inevitably result in enhanced thermal noise, higher power consumption and heat dissipation. In military aircraft, where weight and space are at a premium, these effects are difficult to accommodate. Consequently a method of amplifier linearisation is required that has minimal impact on the power consumption, size and noise figure of the receiver system. A possible solution to this problem, that has recently been advocated, relies on a process termed ‘augmentation’. This solution is explored for application to weakly nonlinear receiver amplifiers and easy-to-use relationships are presented to enable designers to assess the frequency limits of the technique for particular devices and processes. - Author(s): F. Schlögl and H. Zimmermann
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 395 –398
- DOI: 10.1049/ip-cds:20040413
- Type: Article
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p.
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A fully differential low-power operational amplifier in 0.12 μm digital CMOS technology achieving a differential gain of 80 dB is presented. A transit frequency of 20.5 MHz at ±0.7 V supply and with a load of 10 pF has been measured. Owing to an innovative bulk controller for the input transistors, the common-mode input range is larger than ±0.2 V. The operational amplifier can be used down to a supply voltage of ±0.4 V with a differential gain of 63.5 dB. - Author(s): M. Jagadesh Kumar and C.L. Reddy
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 399 –405
- DOI: 10.1049/ip-cds:20040295
- Type: Article
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p.
399
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The authors report a novel method to reduce the collector–emitter offset voltage of the wide bandgap SiC-P-emitter lateral HBTs using a dual-bandgap emitter. In their approach, the collector–emitter offset voltage VCE(offset) is reduced drastically by eliminating the built-in potential difference between the emitter–base (EB) and collector–base (CB) junctions by using a SiC-on-Si P-emitter. It is demonstrated that the proposed dual-bandgap P-emitter HBT, together with the SiGe base and Schottky collector, not only has a very low VCE(offset) but also exhibits high current gain, reduced Kirk effect, excellent transient response and high cutoff frequency. The performance of the proposed device is evaluated in detail using two-dimensional device simulation, and a possible BiCMOS compatible fabrication procedure is also suggested. - Author(s): R. Badard and J.C Commerçon
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 406 –412
- DOI: 10.1049/ip-cds:20040193
- Type: Article
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p.
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The coupling of two Schmitt oscillators has been studied, but no definitive answer is known on the conditions for which they synchronise giving a periodic solution. A complete answer has been given for the particular case of a periodically forced Schmitt oscillator. In this particular case a complete description of the synchronisation domains (sometime called tongues) was given from a type of continued fraction expansion of the winding number. This continued fraction expansion clearly shows the self-similarity of the organisation of the tongues and shows that the measure of the case where the synchronisation does not take place is zero as soon as the coupling exists. It is shown that the more general case can be deduced from the forcing case. In particular it is possible to formally compute the bounds of the domains where the solutions are periodic. When the integration speeds of the oscillators are varied, it is shown that as long as the coupling is dissymmetric the measure of the case where the solutions are not periodic is zero. Such a result is rather counter-intuitive.
Operating limits for distortion reduction by the augmentation technique in nonlinear transistor amplifiers
Low-voltage operational amplifier in 0.12 μm digital CMOS technology
Realising wide bandgap P-SiC-emitter lateral heterojunction bipolar transistors with low collector–emitter offset voltage and high current gain: a novel proposal using numerical simulation
Coupling of two Schmitt oscillators: non-periodic solutions are rare
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- Author(s): Porod Wolfgang and I. Csurgay Árpád
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 413 –414
- DOI: 10.1049/ip-cds:20041170
- Type: Article
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p.
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- Author(s): K.W. Chew ; K.W. Chew ; K.S. Yeo ; S.-F. Chu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 415 –421
- DOI: 10.1049/ip-cds:20040991
- Type: Article
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p.
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This study discusses the composite effect of channel length and gate oxide thickness scaling, coupled with the effect of gate dielectric nitridation on the 1/f noise of minimum channel length NMOS transistors. These transistors have been taken from four advance CMOS technologies with dual gate oxide thickness. The result shows that the current noise spectral density SId of a thin gate oxide transistor increases by approximately 1.5 orders of magnitude when scaling from 350 nm to 130 nm. This increase is closely correlated to the changeover from thermal oxides to nitrided oxides from 250 nm and below. This work also investigates the effect of nitridation on thick gate oxide transistors and compares them to their architecturally equivalent thin gate oxide non-nitrided counterpart from 350 nm technology. The comparison reveals that nitridation has increased the SId of architecturally equivalent thick gate oxide transistors from 250 nm to 130 nm technologies by a maximum of 1.25 orders of magnitude. The experimental 1/f noise trends have been verified with simulations using the BSIM3v3 flicker noise model. - Author(s): A.K. Sharma ; S.H. Zaidi ; S. Lucero ; S.R.J. Brueck ; N.E. Islam
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 422 –430
- DOI: 10.1049/ip-cds:20040993
- Type: Article
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p.
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The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3×) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200 cm2/V s compared to ∼400 cm2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics. - Author(s): S.H. Olsen ; K.S.K. Kwa ; L.S. Driscoll ; S. Chattopadhyay ; A.G. O'Neill
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 431 –437
- DOI: 10.1049/ip-cds:20040995
- Type: Article
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p.
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Strained Si/SiGe heterostructure MOS transistors offer great promise for nanoscale CMOS technology. This paper reviews these high performance devices and the challenges associated with their integration into conventional CMOS processes. Simulation results at a device and circuit level show that n-channel MOSFET performance can influence circuit speed to a greater extent than p-channel devices. Consequently the experimental work discussed is focused on recent progress in the optimisation of strained Si/SiGe n-channel MOSFETs. Simulation predicts that dual channel CMOS architectures offer the greatest performance advantages for both n- and p-channel MOSFETs. However, experimental evidence suggests that a single channel CMOS architecture may be a more pragmatic choice, given the material and processing complexities involved. The optimum SiGe alloy composition for virtual substrate based devices is discussed. Electron mobility is shown to peak in strained Si channels fabricated on relaxed Si0.75Ge0.25, yet wafer yield is compromised for virtual substrate compositions incorporating Ge contents above 15%. Optimum strained Si/SiGe device design is therefore shown to be highly dependent on the device parameter to be optimised, and specific processing conditions. - Author(s): C.H. Hu ; S.D. Cotofana ; J.F. Jiang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 438 –442
- DOI: 10.1049/ip-cds:20040992
- Type: Article
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p.
438
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A digital to analogue converter (DAC) based on a single-electron tunnelling transistor (SETT) is proposed. The proposed scheme fully utilises the Coulomb blockade effect and only a SETT and n+1 capacitors are necessary for an n-bit DAC implementation. Using this scheme, a 4-bit DAC is demonstrated by means of simulation. - Author(s): K.B.K. Teo ; R.G. Lacerda ; M.H. Yang ; A.S. Teh ; L.A.W. Robinson ; S.H. Dalal ; N.L. Rupesinghe ; M. Chhowalla ; S.B. Lee ; D.A. Jefferson ; D.G. Hasko ; G.A.J. Amaratunga ; W.L. Milne ; P. Legagneux ; L. Gangloff ; E. Minoux ; J.P. Schnell ; D. Pribat
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 443 –451
- DOI: 10.1049/ip-cds:20040408
- Type: Article
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p.
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The authors demonstrate the fabrication of solid state and vacuum electronic devices using carbon nanotubes as the active channel and emitters. Single wall and multiwall carbon nanotubes (CNT) are deposited directly on substrates using chemical vapour deposition (CVD) and plasma enhanced chemical vapour deposition (PECVD), respectively. The fabrication of top gate and side gate field effect transistors is demonstrated using single wall CNTs. Vertically aligned multiwall CNTs are used to fabricate field emitter arrays or micro-gated field emitters, which have potential application in field emission displays, microwave amplifiers or electron guns. - Author(s): I.R. Peterson and R.M. Metzger
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 452 –456
- DOI: 10.1049/ip-cds:20040990
- Type: Article
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p.
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The goal of electronic functionality within an individual organic molecule was set many decades ago, but achieving it has not been straightforward. The simple combining rules of chemistry allow an unlimited variety of structures, and it has not been clear which are worth pursuing. It has also not been clear how it might be possible to assemble well-defined nanostructures of usable complexity. While the first steps along this road have required the development of new concepts and have been painfully slow, several milestones have now been passed. The confusion surrounding conduction through ultrathin layers has now been resolved, and stable low-defect two-terminal devices have now been fabricated in which the dominant charge transport is demonstrably through the electroactive organic molecules. Results obtained from these nanostructures will provide basic information about charge transport mechanisms on the molecular scale that will be vital for the future design of high-performance electronic components. - Author(s): S.I. Khondaker
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 457 –460
- DOI: 10.1049/ip-cds:20040957
- Type: Article
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p.
457
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A simple technique is presented for the fabrication of nanoscale devices. Commercially available bare gold colloidal nanoparticles are first trapped between two prefabricated large gap electrodes to form a metallic bridge by the application of an AC electric field. The nanoparticle bridge is then broken by slowly ramping a DC voltage across the junction until the current drops to zero. This simple, highly reliable and reproducible technique consistently produces metallic electrodes with less than 10 nm gap and can be applied to prefabricated electrodes up to 1 μm separation. The nanogaps created are ideally suited to contacting individual nanostructures. The paper describes an electrical transport study of a thiol coated 3 nm gold nanoparticle that shows a clear Coulomb staircase. - Author(s): A.V. Nabok ; J. Massey ; S. Buttle ; A.K. Ray
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 461 –465
- DOI: 10.1049/ip-cds:20040994
- Type: Article
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p.
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A non-destructive technique employing a mercury probe as a counter electrode was successfully developed in order to study the mechanism of charge transport through thin polymer films on silicon and aluminum substrates. The polyelectrolyte self-assembly technique was employed to form the organic films. Both DC and AC current–voltage characteristics were measured at room temperature. An exponential dependence of the tunnelling current on the film thickness was found, and a tunnelling coefficient of 3.3×10−9 m−1 was calculated. The observed voltage dependence was interpreted in terms of the model of a trapezoidal-triangular barrier. The peak in current–voltage characteristics of polymer films on aluminum substrates may be attributed to resonance tunnelling via surface states on the alumina/polymer film interface. - Author(s): O. Marinov ; M.J. Deen ; J. Yu ; G. Vamvounis ; S. Holdcroft ; W. Woods
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 466 –472
- DOI: 10.1049/ip-cds:20040916
- Type: Article
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p.
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The low-frequency noise (LFN) properties of the polymer field effect transistors (PFETs) using polymer semiconducting material are investigated and discussed in terms of the charge carrier transport. Results obtained from several research groups are summarised. A general trend of proportionality between noise power density and the DC power applied to the PFET channel is observed in the data from publications. This trend implies that the mobility fluctuation in the PFET is the dominant noise source. - Author(s): M. Macucci ; G. Iannaccone ; L. Bonci ; M. Girlanda
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 473 –479
- DOI: 10.1049/ip-cds:20040475
- Type: Article
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p.
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The authors discuss the importance of hierarchical modelling for the evaluation of nanoelectronic architectures, with specific reference to quantum cellular automata and molecular devices. Models at different levels of approximation are presented, focusing on their interrelationships and possibilities of further integration. - Author(s): M.C.B. Parish and M. Forshaw
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 480 –485
- DOI: 10.1049/ip-cds:20040746
- Type: Article
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p.
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Single-domain nanomagnets could potentially be used as magnetic logic elements. In this paper, the performance of magnetic cellular automaton (MCA) systems is assessed. The three main types are described briefly and one is analysed in detail. A micromagnetic model which uses Monte Carlo/Metropolis updating is described and shown to be able to reproduce room temperature experimental results. It is subsequently used to investigate a range of MCA system parameters. Emphasis is placed on the potential behaviour of real systems (those which operate at room temperature and which possess fabrication defects). It is found that real adiabatically clocked magnetic systems are likely to operate significantly more slowly than the previously projected limits. - Author(s): L.W. Ji ; Y.K. Su ; S.J. Chang ; S.C. Hung ; C.S. Chang ; L.W. Wu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 486 –488
- DOI: 10.1049/ip-cds:20040997
- Type: Article
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p.
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InGaN/GaN blue light-emitting diodes (LEDs) with self-assembled quantum dot (SAQD) active layers were successfully fabricated using an interrupted growth method in metal-organic chemical vapour deposition (MOCVD). Nanoscale QDs have been formed successfully embedded in quantum wells (QWs) with a typical 3 nm height and 10 nm lateral dimension. A huge 68.4 meV blue shift in electroluminescence (EL) peak position was found as the injection current was increased from 3 to 50 mA for the SAQD LED. The large EL blue shift reveals that deep localisation of exitons (or carriers) originating from QDs strengthens the band-filling effect as the injection current increases. - Author(s): S.R.P. Silva ; J.D. Carey ; G.Y. Chen ; D.C. Cox ; R.D. Forrest ; C.H.P. Poa ; R.C. Smith ; Y.F. Tang ; J.M. Shannon
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 5, p. 489 –496
- DOI: 10.1049/ip-cds:20040996
- Type: Article
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p.
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The holy grail in terms of flat panel displays has been an inexpensive process for the production of large area ‘hang on the wall’ television that is based on an emissive technology. Electron field emission displays, in principle, should be able to give high quality pictures with good colour saturation, and, if suitable technologies for the production of cathodes over large areas were to be made available, at low cost. This requires a process technology where temperatures must be maintained below 450°C throughout the entire production cycle to be consistent with the softening temperature of display glass. In this paper we propose three possible routes for nanoscale engineering of large area cathodes using low temperature processing that can be integrated into a display technology. The first process is based on carbon nanotube–polymer composites that can be screen printed over large areas and show electron field emission properties comparable with some of the best aligned nanotube arrays. The second process is based on the large area growth of carbon nanofibres directly onto substrates held at temperatures ranging from room temperature to 300°C, thereby making it possible to use inexpensive substrates. The third process is based on the use of excimer laser processing of amorphous silicon for the production of lithography-free large area three terminal nanocrystalline silicon substrates. Each route has its own advantages and flexibility in terms of incorporation into an existing display technology. The harnessing of these synergies will be highlighted together with the properties of the cathodes developed for the differing technologies.
Editorial: Nanoelectronics
Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors
Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs
Design, fabrication and characterisation of strained Si/SiGe MOS transistors
Digital to analogue converter based on single-electron tunnelling transistor
Carbon nanotube technology for solid state and vacuum electronics
Towards individual molecules as electronic components
Fabrication of nanoscale device using individual colloidal gold nanoparticles
Study of electron tunnelling through thin polymer films using a mercury probe technique
Low-frequency noise in polymer thin-film transistors
Hierarchical tools for the simulation of nanoscale circuits and devices: from artificial to real molecules
Magnetic cellular automata (MCA) systems
Nitride-based light-emitting diodes with InGaN/GaN SAQD active layers
Nanoengineering of materials for field emission display technologies
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