IEE Proceedings - Circuits, Devices and Systems
Volume 151, Issue 2, April 2004
Volumes & issues:
Volume 151, Issue 2
April 2004
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- Author(s): P.V. Brennan and R. Walkington
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 69 –73
- DOI: 10.1049/ip-cds:20040189
- Type: Article
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The paper describes a new approach to sigma–delta fractional-N frequency synthesis based on the storage of pre-generated bitstreams. By exploiting the nature of frequency hopping systems, fabrication of a hardware sigma–delta modulator can be avoided completely and instead an optimised sigma–delta sequence for each required channel is stored in fast memory. This allows reference frequencies of several hundred MHz, which provides a significant increase in the noise spreading performance of the modulator. The paper describes simulation and implementation of such a synthesiser. Both modelled and measured results are shown to demonstrate that a substantial improvement in performance is possible. - Author(s): J. Bayard
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 74 –77
- DOI: 10.1049/ip-cds:20040162
- Type: Article
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p.
74
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An LC sinusoidal oscillator that requires only three transistors and some passive components is presented. Contrary to the usual method which requires the use of a variable-capacitance (varicap) diode to control the oscillation frequency value, this frequency value is controlled here through a grounded resistor. Another grounded resistor independently controls the condition of the oscillation. Measurements on a prototype that confirm the theoretical analysis are included. - Author(s): V.H. Champac and V. Avendaño
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 78 –82
- DOI: 10.1049/ip-cds:20040431
- Type: Article
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p.
78
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Data retention faults in CMOS SRAMs are tested by sensing the voltage at the data bus lines. Sensing the voltage at one of the data bus lines with proper DFT (design for testability) reading circuitry allows the fault-free memory cells to be discriminated from the defective cell(s). Two required DFT circuitries for applying this technique are proposed. The cost of the proposed approach in terms of area, test time and performance degradation is analysed. A CMOS memory array with the proposed DFT circuitries has been designed and fabricated. The experimental results show the feasibility of this technique. - Author(s): W. Liu ; W. Liu ; S.-K. Wei
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 83 –86
- DOI: 10.1049/ip-cds:20040111
- Type: Article
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83
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New CMOS exponential-control variable-gain amplifiers (VGAs) are presented. The control signal can be either current-mode or voltage-mode. Since no multiplier is needed in the proposed circuits, the proposed VGAs can be very compact. For the case of supply voltages VDD=∣VSS∣=1.5 V, the power dissipation is only 0.48 mW. The gain control range of the proposed VGA can be 30 dB. The proposed circuits have been fabricated in a 0.5 μm n-well CMOS process. Experimental results are given to confirm the feasibility of the proposed VGAs, which are expected to be useful in analogue signal processing applications. - Author(s): K.M. Ku ; K.J. Ha ; K.Y. Yoo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 88 –92
- DOI: 10.1049/ip-cds:20040161
- Type: Article
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p.
88
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AB2 multiplication over GF(2m) is an essential operation in modular exponentiation, which is the basic computation for most public key cryptosystems. The authors present a new architecture that can perform AB2 multiplication over GF(2m) in m clock cycles using cellular automata. The proposed cellular automata architecture is also well suited to VLSI implementation because it is simple, regular, modular, and cascadable.
Stored-sequence sigma–delta fractional-N synthesiser
Single grounded resistance tuneable sinusoidal oscillator
Test of data retention faults in CMOS SRAMs using special DFT circuitries
CMOS exponential-control variable gain amplifiers
Design of new AB2 multiplier over GF(2m) using cellular automata
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- Author(s): M. Jamal Deen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 93 –94
- DOI: 10.1049/ip-cds:20040556
- Type: Article
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p.
93
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- Author(s): M. Marin ; M.J. Deen ; M. de Murcia ; P. Llinares ; J.C. Vildeuil
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 95 –101
- DOI: 10.1049/ip-cds:20040509
- Type: Article
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The impact of body biasing on the low frequency noise (LFN) performances of MOS transistors from a 130 nm CMOS technology was investigated. The body-to-source voltage VBS was varied from –0.5 V to +0.5 V for reverse and forward mode substrate biasing. Detailed electrical characterisation was performed and the benefits of the body bias analysed in terms of current and maximum transconductance variations. Noise measurements were first performed at low drain bias VDS=±25 mV and VBS=0 V in order to discuss the noise origin in the devices. Results are in agreement with the carrier number fluctuation theory ΔN for NMOS and with the correlated carrier number–mobility ΔN–Δμ model for PMOS. Bulk bias dependence of the LFN was investigated at VDS=VDD=±1.2 V. Significant noise reduction of about 50% in both N and PMOSFETS was observed in the weak inversion regime when applying a forward body bias. In strong inversion, the noise level was found to be approximately independent of the substrate bias VBS. An explanation of the main noise results based on McWhorter's number fluctuation theory is proposed. - Author(s): M. Valenza ; A. Hoffmann ; D. Sodini ; A. Laigle ; F. Martinez ; D. Rigaud
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 102 –110
- DOI: 10.1049/ip-cds:20040459
- Type: Article
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p.
102
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An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the ΔN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs. - Author(s): J. Jomaah and F. Balestra
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 111 –117
- DOI: 10.1049/ip-cds:20040109
- Type: Article
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111
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The low-frequency noise (LFN) in partially- and fully-depleted SOI CMOS technologies is overviewed. The static performances and the drain current noise in both linear and saturation regimes are presented for different SOI architectures. Particular attention is paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise. The behaviour of this effect with the frequency and the physical mechanisms explaining this excess noise, are discussed. The control of this noise overshoot by using a body contact or by applying a back gate voltage is also demonstrated. Also, LFN in DTMOS (dynamic threshold MOS) with the body connected to the gate is studied. The use of a clamping transistor as a body current limiter results in excess Lorentzian-like noise, which is similar to the noise induced by the kink effect. Finally, the influence of the gate leakage in an SOI MOS with thin oxide is shown. - Author(s): H.D. Xiong ; D.M. Fleetwood ; J.R. Schwank
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 118 –124
- DOI: 10.1049/ip-cds:20040432
- Type: Article
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p.
118
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The back channel low-frequency noise of 1.2 μm×2.3 μm SOI nMOS transistors with a buried oxide thickness of 170 nm was measured as a function of frequency, back gate bias Vbg and temperature T. For a temperature range of 85≤T≤320 K, noise measurements were performed at frequencies of 0.3≤f≤1 kHz with top gate bias Vbg=0 V and Vbg−Vbg−th=4 V, where Vbg−th is the back gate threshold voltage. The temperature and frequency dependences of the 1/f noise of back channel SOI nMOS transistors show thermally activated charge exchange between the Si channel and defects in the buried oxide. Comparison is made with the Dutta and Horn model of 1/f noise. Devices on one particular wafer appear to show a mixture of 1/f noise and noise with a higher frequency exponent at low temperatures. Little change is observed in back gate noise with irradiation for the devices and irradiation conditions studied. This is probably due to large preirradiation defect densities in the buried oxides. - Author(s): M.J. Deen ; M.J. Deen ; F. Pascal
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 125 –137
- DOI: 10.1049/ip-cds:20040106
- Type: Article
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125
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For many analogue integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. The authors briefly review why bipolar transistors are still of great interest and in widespread use in analogue integrated circuits. The review includes a comparison between BJTs and MOSFETs using a simple small-signal equivalent circuit with important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low-frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. After a review of the effects of different processing technologies and conditions on the noise performance of PE-BJTs, a summary of some of the key technological steps and device parameters and their effects on noise is presented. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low-frequency noise in ultrasmall geometries is a serious issue since the rate of increase of the noise dispersion is faster than that of the noise itself as the emitter geometry is scaled to smaller values. The same effect, but to a greater extent, is also observed in MOSFETs. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe or SiGeC heterojunction bipolar transistors and MOSFETs, are presented after the conclusions. - Author(s): F. Pascal ; C. Chay ; M.J. Deen ; S. G-Jarrix ; C. Delseny ; A. Penarier
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 138 –147
- DOI: 10.1049/ip-cds:20040505
- Type: Article
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The low-frequency noise characteristics of double self-aligned InP/InGaAs and two types of Si/SiGe heterojunction bipolar transistors (HBTs) were investigated. Spectral analysis shows no striking differences; the spectra are composed of a 1/f component and the white noise is always reached at low biases. A general trend for all the transistors was the presence of Lorentzian component(s) for the smallest devices. The voltage coherence function was always unity for SiGe transistors; and for the first time, it was found to be close to zero for InP devices. Concerning the 1/f noise level, both types of transistors have approximately a quadratic dependence on base current bias and an inverse dependence on the emitter area. Thus, a comparison of the 1/f noise level has been made using the Kb parameter, and values around 10−9 μm2 for SiGe HBTs and around 10−8 μm2 for InP HBTs were found. These results are of the same order of magnitude as the best published ones. The low-frequency noise results suggest that excess noise sources are mainly located at the intrinsic emitter–base junction for the two types of SiGe devices, and, for the InP HBTs, a correlated noise source is located at the emitter periphery. To compare different devices and technologies, fc/fT was studied as a function of collector current density and for some HBT technologies fc/fT∝Jc (fc is corner frequency at which the white noise and 1/f noise are equal and fT is the unity current gain frequency). The effects of different processing conditions, designs and temperature were also investigated and discussed. - Author(s): A. Matulionis and J. Liberis
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 148 –154
- DOI: 10.1049/ip-cds:20040199
- Type: Article
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p.
148
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Recent investigation of microwave noise of nominally undoped AlGaN/GaN channels is reviewed. The noise is agitated in a two-dimensional electron gas by an electric field applied in the plane of electron confinement. The experimental results are compared with those of Monte Carlo simulation and with simple semi-empirical formulas. The importance of hot-phonon effects is emphasised. - Author(s): A.-S. Porret ; C.C. Enz ; C.C. Enz
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 155 –166
- DOI: 10.1049/ip-cds:20040436
- Type: Article
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A non-quasi-static (NQS) thermal noise model of the MOS transistor is presented that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are also affected. All prior publications on the subject only deal with IGN in the strong inversion regime. It is shown that significant differences are obtained for moderate and weak inversion operation. A brief review is given of the NQS model valid in all modes of operation. The general thermal noise model using four noisy current sources is described. The power spectral and cross-power spectral densities of these noise sources are computed. A first-order approximation is then derived and compared to the complete model. It is shown that the correlation coefficient between the drain and the gate noise is always null in triode (VD=VS), and varies in saturation between j 0.6 in weak inversion to j 0.4 in strong inversion. To the authors' knowledge, it is the first time that a complete HF thermal noise model of the MOST is presented, that is valid in all modes of inversion and up to and above the NQS cut-off frequency. The impact of this complete NQS noise model on RF-CMOS circuit design is illustrated by two examples. - Author(s): A.J. Scholten ; L.F. Tiemeijer ; R. van Langevelde ; R.J. Havens ; A.T.A. Zegers-van Duijnhoven ; R. de Kort ; D.B.M. Klaassen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 167 –174
- DOI: 10.1049/ip-cds:20040373
- Type: Article
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The thermal noise of short-channel NMOS transistors in a commercially available 0.13 -μm CMOS technology is studied. The experimental results are modelled with a non-quasi-static RF model, based on the principle of channel segmentation. The model is capable of predicting both drain and gate current noise accurately, without fitting any parameters to the measured noise data. An essential ingredient of the model is the gate resistance, which is shown to dominate the gate current noise. In the optimised device layouts, this gate resistance is mainly determined by the silicide-to-polysilicon contact resistance. - Author(s): P.J. Edwards
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 175 –183
- DOI: 10.1049/ip-cds:20040464
- Type: Article
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p.
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The evolution of conceptual models of recombination noise generation in bipolar semiconductor junctions is explored with particular reference to recent developments in non-classical light generation. This development is traced from the early work pioneered by van der Ziel through to recent work on sub-Poissonian light generation initiated by Yamamoto. This recent work has emphasised the importance of the driving impedance in suppressing recombination noise. It has helped to resolve several longstanding ambiguities and misunderstandings concerning the fundamentals of shot noise generation in laser diodes and light-emitting diodes, as well as in bipolar junction diodes and transistors, and allows a common conceptual approach to shot noise generation and propagation in photonic and electronic devices. Surprisingly, it also lends support to early suggestions by van der Ziel, subsequently regarded as erroneous by Buckingham and Faulkner, that bipolar junction shot noise does in fact originate in the transport of minority carriers across the depletion region of macroscopic junctions, although only in the limit of low injection. - Author(s): C.W. Zhang ; X.Y. Wang ; L. Forbes
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 184 –189
- DOI: 10.1049/ip-cds:20040435
- Type: Article
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Timing jitter is a concern in high frequency oscillators; the presence of timing jitter will degrade system performance in many high speed applications. In the first part of the paper, the authors have simulated the timing jitter due to CMOS device noise in a nine-stage CMOS differential ring oscillator, and a methodology to efficiently simulate timing jitter has been developed. Simulation results show that the variation of absolute jitter due to flicker noise has t-dependence while for white noise it has t0.5-dependence; these are consistent with accepted theory. Two important parameters, cycle jitter and cycle-to-cycle jitter, used to describe jitter performance can be obtained from simulation. Simulation results are also compared with measurement results, and it is shown that simulation results are very close to measurement results. All these serve to verify the validity of this technique. In the second part of the paper, the authors have employed this methodology and investigated the timing jitter in silicon BJT/or SiGe HBT ECL ring oscillators, and they have shown that BJT/or SiGe HBT oscillators have lower jitter compared to their CMOS counterparts. The methodology described in the paper is also applicable to other types of clock generator and oscillators such as LC oscillators, as well as other kinds of noise source such as power supply and substrate noise. - Author(s): L.B. Kish
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 151, Issue 2, p. 190 –194
- DOI: 10.1049/ip-cds:20040434
- Type: Article
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p.
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It has recently been recognised that speed, noise and energy dissipation are strongly interrelated entities. Following Moore's law of miniaturisation, at sizes below 40 nm, physics will impose fundamental and practical limits of performance by shrinking noise margin, increasing and quickening noise, and increasing power dissipation. It is important to locate the fundamental aspects of the problem, explore relevant practical problems and possible solutions, and investigate this situation, not only in microelectronics (CMOS etc.) but also in single-electron-transistor-based nanoelectronics and also in quantum informatics applications. The energy requirement of running classical and quantum logic gates is compared.
Editorial: Noise in devices and circuits
Effects of body biasing on the low frequency noise of MOSFETs from a 130 nm CMOS technology
Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm
Low-frequency noise in advanced CMOS/SOI devices
Low-frequency noise and radiation response of buried oxides in SOI nMOS transistors
Review of low-frequency noise behaviour of polysilicon emitter bipolar junction transistors
Comparison of low-frequency noise in III–V and Si/SiGe HBTs
Microwave noise in AlGaN/GaN channels
Non-quasi-static (NQS) thermal noise modelling of the MOS transistor
Compact modelling of noise for RF CMOS circuit design
Recombination noise in semiconductor junction devices
Simulation technique for noise and timing jitter in electronic oscillators
Moore's law and the energy requirement of computing versus performance
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