IEE Proceedings - Circuits, Devices and Systems
Volume 150, Issue 3, June 2003
Volumes & issues:
Volume 150, Issue 3
June 2003
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- Author(s): M. Hasan and T. Arslan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 149 –154
- DOI: 10.1049/ip-cds:20030347
- Type: Article
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p.
149
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The authors present a novel order-based coefficient processing scheme for the realisation of low-power FFT processors. The scheme is based on the minimisation of the Hamming distance between successive coefficients fed to the butterfly. A distinct feature of the scheme that distinguishes it from conventional order-based schemes lies in the fact that either the real part of the coefficient or its two's complemented value is used for the minimisation of the Hamming distance between successive coefficients and hence the switching activity. The paper describes the scheme and its implementation, and provides results using a number of fully synthesised FFT processor cores. The results demonstrate that the switching activity is reduced by up to 53% for different FFT lengths compared to only 27% when conventional order-based processing is employed. This significant reduction in switching activity leads to power savings in the range of 25% to 1% for different FFT processor cores. - Author(s): A.T. Erdogan ; M. Hasan ; T. Arslan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 155 –160
- DOI: 10.1049/ip-cds:20030346
- Type: Article
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p.
155
–160
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The authors present a number of novel architectures for the implementation of low power FIR filtering cores. These architectures are directly translated from flexible algorithms which exploit data and coefficient correlation in order to minimise the effective switched capacitance on the multiplier, and data/coefficient buses. Another characteristic of these algorithms is that they can be combined to form more power-efficient algorithms which in turn could be mapped to more effective architectures. The paper describes the FIR filtering architectures, the arithmetic processing cores which characterise individual architectures, and provides results which demonstrate up to 39% reduction in power. In addition, the paper provides an analysis of the arithmetic processing cores and the impact of their constituent components on the overall power saving with different algorithms. - Author(s): S. Mohammadi ; S. Furber ; J. Garside
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 161 –166
- DOI: 10.1049/ip-cds:20030349
- Type: Article
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p.
161
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Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits. - Author(s): W. Kuang ; J.S. Yuan ; R.F. DeMara ; M. Hagedorn ; K. Fant
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 167 –172
- DOI: 10.1049/ip-cds:20030343
- Type: Article
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p.
167
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A self-timed ring using NULL convention logic (NCL) is presented. An analytical method to evaluate the speed of NCL rings has been developed. The analytical predictions are verified by a Synopsys simulation and excellent agreement between the theoretical predictions and simulation results is obtained. Some important principles for ring optimisation are obtained. The analysis leads to the speed optimisation of a 24-bit NCL divider. - Author(s): G.T. Zardalidis and I. Karafyllidis
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 173 –177
- DOI: 10.1049/ip-cds:20030345
- Type: Article
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p.
173
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A single-electron full-adder is presented in which bits of information are represented by the presence or absence of single electrons at conducting islands. The logic operation of the full-adder is verified using simulation, and the stability of its operation is analysed using a Monte Carlo method. - Author(s): A.A. Hiasat
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 179 –184
- DOI: 10.1049/ip-cds:20030339
- Type: Article
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p.
179
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Two new structures for digital sweep oscillators are presented. The first oscillator overcomes the limitations associated with previously reported oscillators. The second proposed oscillator provides the features of the first, while being capable of generating very low sweep-rate signals. The sweep rates produced by this oscillator can be orders of magnitude less than those reported by Hiasat and Al-Khateeb (1998). As demonstrated by simulation results, the performance of the proposed oscillators is substantially better than other reported systems. - Author(s): F. Fiori and P.S. Crovetti
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 185 –193
- DOI: 10.1049/ip-cds:20030342
- Type: Article
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p.
185
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The authors present a new analytical model that describes the nonlinear behaviour of common CMOS operational amplifiers excited by radio-frequency interference (RFI) added to the input nominal signals. The new model is a valid support to analogue integrated circuit designers since it expresses a relationship between circuit parameters, parasitic elements and the amplitude of the RFI induced output offset voltage of a feedback CMOS operational amplifier. The validity of model prediction has been verified through a comparison with experimental and computer simulation results. - Author(s): G. Palmisano and S. Pennisi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 194 –198
- DOI: 10.1049/ip-cds:20030352
- Type: Article
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p.
194
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The paper addresses the design of CMOS amplifiers with inherent single-to-differential conversion for use in high-frequency applications. Design techniques for stabilising the operating point and providing substantial increase in gain and/or bandwidth performance are also discussed. Simulations on designs using a 0.8-μm technology are provided confirming the accuracy of the expected performance. - Author(s): F. Ellinger and W. Bächtold
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 199 –204
- DOI: 10.1049/ip-cds:20030341
- Type: Article
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p.
199
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Active, monolithically integrated S-band (1.1 GHz→2.2 GHz) and C-band (2.2 GHz→4.4 GHz) frequency/phase doublers with ultra-compact circuit areas of less than 0.6 mm2 and 0.5 mm2, respectively, are presented using a commercial 0.6 μm gallium arsenide (GaAs) metal semiconductor field effect transistor (MESFET) technology. These circuits were designed for low-power-consuming adaptive antenna receivers, operating in accordance with the high-performance radio local area network (HIPERLAN) and 802.11a standards. Cascading of the two doublers enables phase control range quadruplication of low cost phase shifters with 90° phase control range in the local oscillator (LO) path. Thus, a phase control range of 360° with low amplitude variations is reached in the radio frequency (RF) path, as required for adaptive antenna combining. Simulations performed using the modified MESFET large signal model show excellent agreement with measured results. At an ultra-low supply voltage of 0.9 V, a supply current of 5.8 mA and an input power of only −8 dBm, a conversion gain of 0.5 dB was measured for the quadrupler circuit. To the knowledge of the authors, the circuits present the best results for frequency multipliers in terms of power consumption and miniaturisation, reported to date. - Author(s): S. Pennisi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 205 –209
- DOI: 10.1049/ip-cds:20030350
- Type: Article
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p.
205
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A CMOS current operational amplifier (COA) is exploited to obtain a voltage amplifier operating at 1 V and with an input bias voltage of 0.5 V. The COA employs a class AB input stage that enhances the slew-rate performance and provides accurate control of both the quiescent currents and the input bias voltage. It exhibits a 56-dB loop gain with a gain–bandwidth product of 18 MHz. Based on this COA, a 1-V voltage amplifier is implemented. It provides a constant closed-loop bandwidth of about 2 MHz and exhibits a THD better than –60 dB for a 1-MHz 600-mVpp output signal. - Author(s): M. Rizzi ; V. Antonicelli ; B. Castagnolo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 210 –216
- DOI: 10.1049/ip-cds:20030344
- Type: Article
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p.
210
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The performance of a GaAs semiconductor matrix pixel detector, designed for intrinsic digital radiography, is evaluated. Electrical characterisation of different pixels is realised and a new numerical model is indicated for the charge and the current due to electron/hole pairs generated by the ionising radiation. The model, taking into account trapping and generated carrier phenomena, allows the indirect evaluation of the charge collection efficiency through a preliminary determination of the real trap distribution and transport parameters depending on the electric field. The numerical simulations obtained, confirming the electrical behaviour, make a more accurate design of the electronic front-end possible. - Author(s): Y. Chung
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 217 –226
- DOI: 10.1049/ip-cds:20030351
- Type: Article
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p.
217
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A new FRAM architecture utilising a grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: a VDD-precharged bit-line, a negative-voltage word-line technique and negative-pulse restoration. Because this configuration does not need the plate control circuitry, it greatly increases the memory cell efficiency. In addition, unlike other reported common-plate cells, this scheme can supply a sufficient voltage of VDD to the ferroelectric capacitor while detecting and storing the polarisation on the cell. Thus, there is no restriction on low-voltage operation. Furthermore, by employing a compact column-path circuitry which only activates the required 8-bit data, this architecture minimises the current consumption of the memory array. A 2.5-V, 2-Mbit prototype chip has been developed with 0.5-μm CMOS technology, and the possibility of the realisation of GPPG cell architecture has been confirmed. - Author(s): A.M. Sommariva
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 150, Issue 3, p. 227 –231
- DOI: 10.1049/ip-cds:20030348
- Type: Article
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p.
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Closing an ideal switch between two passive linear lumped time-invariant capacitors with different initial voltages gives rise to an apparent paradox. A part of the total energy stored in the two capacitors suddenly vanishes, but, seemingly, the switch cannot account for this loss. Hence, the energy conservation law appears to be violated. The author reconsiders this circuit, and gives a complete explanation of it based on a new embedding of the switch model. The embedding consists of a family of smooth switches with a finite transition time, and therefore is much more general and more realistic than the standard model. Furthermore, the asymptotic analysis carried out not only shows that the switch accounts for the energy loss (and thus the energy conservation law is not violated), but also explains the mechanisms underlying the behaviour of the circuit.
Implementation of low-power FFT processor cores using a novel order-based processing scheme
Algorithmic low power FIR cores
Designing robust asynchronous circuit components
Performance analysis and optimisation of NCL self-timed rings
Design and simulation of a single-electron full-adder
New digital sweep oscillator structures
Prediction of EMI effects in operational amplifiers by a two-input Volterra series model
CMOS single-input differential-output amplifier cells
Compact and low power consuming frequency/phase multiplier MMICs for wireless LAN at S-band and C-band
Low-voltage CMOS current amplifier and its use for high-performance voltage amplification
New model for a GaAs X-ray pixel detector
High performance ferroelectric memory with grounded-plate PMOS-gate cell technology
Solving the two capacitor paradox through a new asymptotic approach
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