IEE Proceedings - Circuits, Devices and Systems
Volume 148, Issue 3, June 2001
Volumes & issues:
Volume 148, Issue 3
June 2001
-
- Author(s): M.H. Capstick and J.K. Fidler
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 109 –114
- DOI: 10.1049/ip-cds:20010288
- Type: Article
- + Show details - Hide details
-
p.
109
–114
(6)
It is shown that the original definition of e developed by Euler can be used as the basis of a delay approximation where all the poles have the same value. Furthermore, it is demonstrated that by splitting the Euler function into complex pole pairs, by the addition of an artificial variable β, an additional degree of freedom can be introduced. Through optimisation of the value of β it is shown that either the group delay or step response can be optimised. This delay approximation, when compared to a standard Bessel approximation, is shown to provide acceptable performance for many applications. Furthermore, it offers the considerable practical benefit of being realisable as a cascade of identical building block elements when appropriate technologies (e.g. second-order active filter blocks) are used. - Author(s): S. Özoğuz ; C. Acar ; A. Toker ; E.O. Güneş
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 115 –120
- DOI: 10.1049/ip-cds:20010193
- Type: Article
- + Show details - Hide details
-
p.
115
–120
(6)
Two transformation methods for obtaining new topologies from a given current-mode CCII filter are presented. These topologies realise the same transfer function as the initial filter for ideal CCIIs, but they can be derived in such a way that their active sensitivity with respect to a particular active parameter becomes zero. In this way, from a filter suffering from large active sensitivities, one may systematically obtain new filters with better active sensitivities. - Author(s): K. Uesaka and M. Kawamata
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 121 –125
- DOI: 10.1049/ip-cds:20010342
- Type: Article
- + Show details - Hide details
-
p.
121
–125
(5)
The authors propose a new approach to the synthesis of low coefficient sensitivity second-order digital filter sections using genetic programming (GP). GP is applied to the synthesis problem by establishing a mapping between the filter structures and computer programs. Genetic operators change the computer programs in order to change the connections between the elements in the filter structures, and consequently change the coefficient sensitivities of those filter structures. The fitness measure that includes the coefficient sensitivities enables the selection operator to choose low sensitivity filter structures. In the paper, two coefficient sensitivity measures are used: the magnitude sensitivity and the relative sensitivity. A numerical example is presented to demonstrate that the sensitivity of the filter synthesised by GP is lower than that of other low coefficient sensitivity filter structures proposed so far. - Author(s): K. Galkowski ; E. Rogers ; A. Gramacki ; J. Gramacki ; D.H. Owens
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 126 –134
- DOI: 10.1049/ip-cds:20010341
- Type: Article
- + Show details - Hide details
-
p.
126
–134
(9)
Repetitive processes are a distinct class of 2-D systems of both practical and algorithmic interest. The paper gives some important new results on the analysis and control of the sub-class known as discrete linear repetitive processes in the presence of a general set of pass initial conditions, which are termed boundary conditions here. These results consist of stability tests which can be implemented by direct application of standard (or 1-D) linear systems tests and the use of control action to decouple the effects of the boundary conditions. - Author(s): D.P. Andrews and C.S. Aitchison
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 135 –139
- DOI: 10.1049/ip-cds:20010346
- Type: Article
- + Show details - Hide details
-
p.
135
–139
(5)
Analytic solutions to the transfer functions required for lumped element quadrature hybrids are derived. These transfer functions are necessary for the synthesis of circuits with optimum Chebychev responses to the through and coupled ports. It is found that high-order functions can be derived with very little computational effort. - Author(s): S.-I. Liu ; T.-B. Yu ; H.-W. Tsao
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 141 –144
- DOI: 10.1049/ip-cds:20010158
- Type: Article
- + Show details - Hide details
-
p.
141
–144
(4)
A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6 µm single-poly double-metal (SPDM) CMOS process and its core area is 0.95 × 1.1 mm2. The maximum operating frequency is 85 MHz. For a 10 MHz sinusoidal output, the phase noise is –114 dBc/Hz at an offset frequency of 10 kHz. The measured SNR is 60.77 dB and worst case spurious is –67.6 dBc. Its power dissipation is 80 mW at 80 MHz under the 5 V supply. - Author(s): J. Da̧browski
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 145 –150
- DOI: 10.1049/ip-cds:20010125
- Type: Article
- + Show details - Hide details
-
p.
145
–150
(6)
The application of waveform relaxation to the piecewise linear (PWL) macro-simulation technique is considered. It is oriented towards functional-level analogue and mixed-signal structures of A/D networks. The main issues in the actual PWL approach are briefly described. The waveform relaxation-based PWL algorithm is formulated in terms of a mathematical network model, and the convergence proof for it is given. Different feedback loops faced in analogue and mixed A/D networks are discussed with respect to the algorithm convergence. Macro-simulation examples of practical use illustrating the presented approach are also included. - Author(s): S. Kim ; J. Kim ; S.-Y. Hwang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 151 –156
- DOI: 10.1049/ip-cds:20010343
- Type: Article
- + Show details - Hide details
-
p.
151
–156
(6)
The authors propose an efficient path balancing algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm employs gate sizing and buffer insertion methods to achieve path balancing. The gate sizing technique reduces not only glitches, but also the effective capacitance in the circuit. For the paths which remain unbalanced after gate sizing due to the limitation of gate size, buffer insertion is performed. Since the buffer itself consumes power, it is inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffer. Determining the location of the inserted buffer is a difficult problem, because the power reduction achieved by an inserted buffer is closely related to the locations of the other inserted buffers. The ILP (integer linear program) has been employed to determine the locations of inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5% of glitch reduction and 30.4% of power reduction are achieved without increasing the critical path delay. - Author(s): G.K. Balachandran and P.E. Allen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 157 –164
- DOI: 10.1049/ip-cds:20010128
- Type: Article
- + Show details - Hide details
-
p.
157
–164
(8)
A fully differential switched-current memory cell with low charge-injection errors is proposed. The cell uses constant-voltage switching to obtain signal-independent charge injection, which is rejected using suitable differential structures. The cell is designed using a 0.35 µm digital CMOS process. Simulation results of the cell with a clock frequency of 13 MHz and with input signal amplitudes nearly as high as the bias current (600 µA) show a total harmonic distortion of –66 dB, a current transfer error of less than 0.4% and a signal-to-noise ratio of 60 dB. - Author(s): Y. Singh and M.J. Kumar
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 165 –170
- DOI: 10.1049/ip-cds:20010249
- Type: Article
- + Show details - Hide details
-
p.
165
–170
(6)
The authors report a new Schottky structure, called the lateral merged double Schottky (LMDS) rectifier, which utilises the trenches filled with a high barrier metal to pinch off a low barrier Schottky contact during the reverse bias. Two-dimensional numerical simulation is used to evaluate and compare the performance of the LMDS rectifier with the conventional Schottky and the recently reported lateral merged PiN Schottky (LMPS) rectifier. The authors show that the proposed device provides an order of magnitude reduction in the reverse leakage current and three times higher reverse breakdown voltage when compared to the conventional Schottky rectifier. A significant feature of the LMDS rectifier is that, in spite of having only Schottky junctions, it gives an extremely sharp breakdown similar to that of a PiN diode. It is demonstrated that for forward current densities up to 400 A/cm2, the LMDS rectifier can provide twice the current that can be realised using the LMPS rectifier for a given forward voltage drop. Furthermore, it is shown that even up to an operating temperature of 80°C, power losses in the LMDS rectifier are smaller than those found in the LMPS rectifier. The reasons for the improved performance of the LMDS rectifier are analysed, and design tradeoffs between the forward voltage drop and the reverse leakage current are presented. - Author(s): H. Li and H.-Z. Wu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 148, Issue 3, p. 171 –175
- DOI: 10.1049/ip-cds:20010248
- Type: Article
- + Show details - Hide details
-
p.
171
–175
(5)
The structure of the microgap and the manufacturing processes for a new type of microgap surge absorber, fabricated by semiconductor technology, are described. A very stable spark-over voltage with a narrow distribution was obtained by coating the metallic films in the microgap. As well as the desirable characteristics of common microgap surge absorbers, this new type of microgap surge absorber has other advantages such as small size, low cost and suitability for mass production.
Delay approximation for synchronous filter topologies
Derivation of low-sensitivity current-mode CCII-based filters
Heuristic synthesis of low coefficient sensitivity second-order digital filters using genetic programming
Stability and dynamic boundary condition decoupling analysis for a class of 2-D discrete linear systems
Transfer functions of optimum lumped element quadrature hybrids
Pipeline direct digital frequency synthesiser using decomposition method
Waveform relaxation approach to PWL simulation of analogue and mixed A/D networks at the functional level
New path balancing algorithm for glitch power reduction
Fully differential switched-current memory cell with low charge-injection errors
Novel lateral merged double Schottky (LMDS) rectifier: proposal and design
Electrical characterisations of new microgap surge absorber fabricated by using conventional semiconductor technology
Most viewed content for this Journal
Article
content/journals/ip-cds
Journal
5
Most cited content for this Journal
We currently have no most cited data available for this content.