IEE Proceedings - Circuits, Devices and Systems
Volume 147, Issue 6, December 2000
Volumes & issues:
Volume 147, Issue 6
December 2000
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- Author(s): P.B. Wu ; R.J. Mack ; R.E. Massara
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 313 –318
- DOI: 10.1049/ip-cds:20000775
- Type: Article
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p.
313
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A quantitative benchmarking metric is presented for the evaluation of the quality of analogue layout. It facilitates comparisons between alternative design automation tools and, for a given tool, provides assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net routing optimality. The algorithm has been developed to accommodate hierarchical structures, as well as flat designs. The metric allows the designer to alter the relative importance of area and routing efficiencies, although a recommendation is given on the appropriate balance. The results demonstrate the use of the metric to evaluate an automatic layout tool, and its effectiveness in providing a characterisation that corresponds to the expert designer's judgement. - Author(s): J.B. Grimbleby
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 319 –323
- DOI: 10.1049/ip-cds:20000770
- Type: Article
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p.
319
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Most analogue systems are designed manually because automatic circuit synthesis tools are available for only a limited range of design problems. A new approach to circuit synthesis based on genetic algorithms is presented. Using this method it is possible in principle to synthesise circuits to meet any linear or nonlinear, frequency-domain or time-domain, specification. When applied to existing filter design problems this circuit synthesis method produces design solutions that are more efficient than those resulting from formal design methods or created manually by an experienced analogue circuit designer. - Author(s): H. Jardón-Aguilar and J. Aguilar-Torrentera
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 325 –330
- DOI: 10.1049/ip-cds:20000669
- Type: Article
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p.
325
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An algorithm is installed into the Spice code for simulating AM–PM conversion as a phase statement of compression and desensitisation phenomena. The algorithm is based on a novel model suitable for analysis of the AM–PM conversion introduced by weakly nonlinear circuits. The Berkeley Spice version 3F5 source code was modified to obtain the compression and desensitisation coefficients and the AM–PM conversion in weakly nonlinear circuits as a phase statement of compression and desensitisation effects. Results of the simulation of the AM–PM conversion introduced by a microwave GaAs FET amplifier are reported. - Author(s): K.-L. Chan ; M.-A. Do ; K.-S. Yeo ; J.-G. Ma
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 331 –333
- DOI: 10.1049/ip-cds:20000607
- Type: Article
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To have a fully integrated communication system in CMOS, a CMOS bandpass amplifier which combines the functions of low noise amplifier (LNA) and bandpass filter (BPF) is necessary. In a conventional bandpass amplifier, a Q-enhancement circuit is required to compensate for the resistive loss in the integrated inductor. The Q-enhancement circuit, however, being active, increases the power consumption (Pd) and noise figure (NF) of the system. In the paper, a new bandpass amplifier has been proposed which can achieve the required Q without an additional Q-enhancement circuit. Comparison with other recent designs shows that the proposed amplifier has the lowest Pd and the best noise performance. Based on the CSM 0.25 µm CMOS process, the bandpass amplifier has a gain of 25.3 dB, a Q of 30, an NF of 3.56 dB and a Pd of 35.7 mW at 1.8 GHz. - Author(s): E.M. Cherry
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 334 –346
- DOI: 10.1049/ip-cds:20000633
- Type: Article
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p.
334
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Systematic relations exist between the four basic single-loop feedback amplifier configurations (voltage-gain, current-gain, transfer-admittance and transfer-impedance) and certain newer configurations for which bandwidth is independent of gain. Loop gain provides the link. For a given amplifier without feedback and specified demanded gain, loop gain and hence bandwidth can be maximised by optimum choice of the feedback resistors. For resistors far removed from this optimum, loop gain can remain constant as demanded gain is varied. Clearly defined conditions exist where adding a unity-gain common-collector or common-base stage at the input will increase the loop gain. Shifting the ground point, source or load generates additional feedback amplifier configurations. - Author(s): P. Corsonello ; S. Perri ; G. Cocorullo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 347 –355
- DOI: 10.1049/ip-cds:20000691
- Type: Article
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p.
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Pipelined cellular array implementations of arithmetic circuits are usually adopted to obtain high throughput at reasonable cost. The circuit design style used to implement the array greatly influences both performance and cost. The designer has to move in a varied and complex scenario, since nowadays scores of logic styles are known among CMOS families. Static logic styles are easy to use and they allow low power consumption, while dynamic logic styles have some potential advantages. These circuits tend to be faster and, at least for the implementation of simple logic functions, they require fewer transistors. Often the choice of the circuit design style is done by means of qualitative analysis. Referring to the creation of a pipelined square-rooting circuit, both static and dynamic implementations are quantitatively compared for several operand wordlengths. Using 0.5 µm technology parameters, a pre-layout comparison is performed in terms of net transistor area, number of transistors, propagation delay and average power dissipation. Results indicate that DOMINO logic implementation shows the best area–time–power trade-off. Then a set of standard cells has been designed to layout the DOMINO logic array. Post-layout data shows that a 32-bit array designed in this way and realised using 0.5 µm 3.3 V CMOS process reaches a maximum throughput rate up to 175 MHz, requires a silicon area of 1.4 × 1.4 mm2 and dissipates 1.59 mW/MHz. The proposed RCA-based circuit reaches a throughput comparable to that of CLA-based square-rooting arrays, implemented using conventional static CMOS circuitry, thereby saving area and power. - Author(s): G.F.W. Khoo ; D.R.H. Carter ; R.A. McMahon
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 356 –362
- DOI: 10.1049/ip-cds:20000690
- Type: Article
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p.
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Charge pumps can be used to generate floating voltage supplies owing to their low input to output voltage drop and circuit simplicity. When used to power the high-side circuitry of half-bridges, the charge pump circuit can be simplified significantly by replacing the function of the dedicated pump oscillator with the switching action of the half-bridge output voltage. Three classes of the auto charge pump are identified, and a model is derived for each of the circuits. Using the model, auto charge pump circuits are designed for use in a half-bridge inverter and tested. The tests show a good match between the models and the experimental results. Finally, a comparison of the the various auto charge pump circuits is made. - Author(s): S.M. Mishra ; S.S. Rofail ; S.K. Yeo
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 6, p. 363 –368
- DOI: 10.1049/ip-cds:20000687
- Type: Article
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p.
363
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Double edge-triggered flip-flops (DETFFs) use both edges of the clock to latch data and hence can lead to significant power saving over single edge-triggered flip-flops for a fixed data rate. However, existing DETFF implementations suffer from the problems of charge sharing, charge coupling, incomplete voltage swing, poor voltage scaling properties and excessive power dissipation. A new DETFF is proposed, which does not suffer from any of these problems and can operate at a clock speed which is 1.33 times that of the best double edge-triggered flip-flop available today. With reduced supply voltages, this flip-flop results in lower power dissipation and maintains a comparable performance to, if not better than, existing DETFFs.
Quantitative method for evaluating quality of analogue VLSI layout
Automatic analogue circuit synthesis using genetic algorithms
Spice model for AM–PM conversion introduced by weakly nonlinear circuits
1.5 V 1.8 GHz bandpass amplifier
Feedback amplifier configurations
Performance comparison between static and dynamic CMOS logic implementations of a pipelined square-rooting circuit
Comparison of charge pump circuits for half-bridge inverters
High performance double edge-triggered flip-flop using a merged feedback technique
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