IEE Proceedings - Circuits, Devices and Systems
Volume 147, Issue 2, April 2000
Volumes & issues:
Volume 147, Issue 2
April 2000
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- Author(s): C.A. Looby and C. Lyden
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 93 –99
- DOI: 10.1049/ip-cds:20000030
- Type: Article
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p.
93
–99
(7)
The field-programmable analogue array (FPAA) is crucial to improving turnaround time for analogue circuit designs. The critical parameters when specifying the design are bandwidth and accuracy. FPAAs reported to date compromise one parameter when optimising the other. A new continuous-time FPAA architecture is presented which simultaneously achieves bandwidth and repeatability comparable to the accuracy tolerance of switched-capacitor FPAAs and the bandwidth of continuous-time FPAAs. It uses continuous-time operation for high bandwidth and introduces buffered CMOS pass-switches and ratioed function blocks to overcome accuracy limitations. A prototype circuit is presented and applied to op-amp based circuits. The results show that the new FPAA offers the best combination of bandwidth and accuracy published to date. - Author(s): C. Fiocchi ; U. Gatti ; F. Maloberti
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 100 –106
- DOI: 10.1049/ip-cds:20000200
- Type: Article
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p.
100
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The authors address some fundamental issues in track-and-hold (T&H) design. A number of explicit expressions characterising the main limitations of this class of circuits are given. A fully differential open-loop T&H is presented satisfying the stringent specifications imposed by present telecom applications. It exhibits high-resolution (12 bit) and high-speed (fck = 160 MHz) as measured on samples integrated in a standard 0.8 µm 12-GHz BiCMOS technology. The overall performance is beyond state-of-the-art. The T&H's size is 0.37 mm2, and it consumes 45 mA from a 5 V power supply. - Author(s): M.J. Bellido-Díaz ; J. Juan-Chico ; A.J. Acosta ; M. Valencia ; J.L. Huertas
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 107 –117
- DOI: 10.1049/ip-cds:20000197
- Type: Article
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p.
107
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A delay model for static CMOS gates with application in gate level logic simulation is presented. It incorporates the degradation effect on narrow pulses and is named PID (pure, inertial and degradation). The results lead to the conclusion that the proposed new delay model maintains the high speed of gate-level logic simulation with a precision comparable to that of electrical simulation. - Author(s): W.-D. Tseng and K. Wang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 119 –124
- DOI: 10.1049/ip-cds:20000198
- Type: Article
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p.
119
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The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault coverage, test methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model. - Author(s): H.L. Kwok
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 125 –128
- DOI: 10.1049/ip-cds:20000028
- Type: Article
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p.
125
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(4)
The I–V characteristics of organic thin-film transistors are examined and a model is proposed that could explain the behaviour of the drain current in the ‘subthreshold’ mode. The model proposes that an injection current at the source dominates the ‘subthreshold’ current at positive gate voltage and the magnitude of this current is modulated by space charge residing in the bulk of the thin film. It is further proposed that a guard ring around the source could minimise the injection current. - Author(s): M.M. Shahidul Hassan
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 129 –132
- DOI: 10.1049/ip-cds:20000201
- Type: Article
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p.
129
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Based on the assumption of negligible recombination within the thin epitaxial collector layer of an integrated bipolar transistor switch in quasi-saturation, solutions to the collector minority carrier profile and transit time in the induced base are derived. In contrast to Dai and Yuan's analysis (1997), the present analysis takes both the drift and diffusion currents into account and is valid for all levels of injection. Dependence of transit time on characteristics of the epitaxial–substrate interface and recombination at the interface is studied for the transistor driven into hard saturation. At high effective surface recombination velocity, recombination at the interface cannot be neglected. The study shows that transit time increases more rapidly with collector current when the transistor operates in hard saturation and the interface is highly reflecting. - Author(s): S. Dasgupta and P. Chakrabarti
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 133 –138
- DOI: 10.1049/ip-cds:20000203
- Type: Article
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p.
133
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The effect of radiation-induced changes on the characteristics of an n-channel MOSFET has been investigated theoretically. A one-dimensional semi-numerical model of the device has been developed which can estimate fairly accurate characteristics of the device under unirradiated and irradiated conditions. The effect of ionising radiation on the channel voltage and electric field profile in the channel has been estimated numerically for the first time. The present model enables one to determine the ID/VD and transfer characteristics of the device by considering the field dependent mobility of the surface channel in the irradiated condition. The model presented here can be used as a basic tool for analysing MOS transistors exposed to a nuclear environment. - Author(s): A. Giorgio ; V.M.N. Passaro ; A.G. Perri
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 139 –145
- DOI: 10.1049/ip-cds:20000051
- Type: Article
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p.
139
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An improved DC model of low- and high-power GaAs MESFETs is proposed. Third-order dependence of fitting parameters on bias conditions is included. The main objective is to obtain a very good agreement between measured and simulated I–V curves, particularly in the knee and saturation regions, regardless of the technological characteristics of the device. The model has been compared with the most significant models presented in the literature, showing some significant improvements of the state-of-the-art. - Author(s): R. Venkatraman and A.K.S. Bhat
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 147, Issue 2, p. 146 –152
- DOI: 10.1049/ip-cds:20000177
- Type: Article
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p.
146
–152
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The paper presents large signal transient analysis of a two-switch, soft-switching, single-stage AC-to-DC converter using a discrete time domain analysis approach. Analysis is used to predict the behaviour of the converter for step changes in load and supply voltages. Theoretical results are verified by PSPICE simulation and experimental results.
Op-amp based CMOS field-programmable analogue array
Design issues on high-speed high-resolution track-and-holds in BiCMOS technology
Logical modelling of delay degradation effect in static CMOS gates
Fault coverage and defect level estimation models for partially testable MCMs
Analytical model for current transport in organic thin-film transistors
Analytical base transit time of integrated bipolar transistors in quasi-saturation and hard saturation
Effect of ionising radiation on the characteristics of a MOSFET
DC model of GaAs MESFETs improving circuit simulation
Large-signal transient analysis of a soft-switching, two-switch AC-to-DC converter
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