IEE Proceedings - Circuits, Devices and Systems
Volume 146, Issue 6, December 1999
Volumes & issues:
Volume 146, Issue 6
December 1999
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- Author(s): E.L. Hines ; E. Llobet ; J.W. Gardner
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 297 –310
- DOI: 10.1049/ip-cds:19990670
- Type: Article
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p.
297
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The field of electronic noses, electronic instruments capable of mimicking the human olfactory system, has developed rapidly in the past ten years. There are now at least 25 research groups working in this area and more than ten companies have developed commercial instruments, which are mainly employed in the food and cosmetics industries. Most of the work published to date, and commercial applications, relate to the use of well established static pattern analysis techniques, such as principal components analysis, discriminant function analysis, cluster analysis and multilayer perceptron based neural networks. The authors first review static techniques that have been applied to the steady-state response of different odour sensors, e.g. resistive, acoustic and FET-based. Then they review the emerging field of the dynamic analysis of the sensor array response. Dynamic signal processing techniques reported so far include traditional parametric and nonparametric ones borrowed from the traditional field of system identification as well as linear filters, time series neural networks and others. Finally the authors emphasise the need for a systems approach to solve specific electronic nose applications, with associated problems of sensor drift and interference. - Author(s): V.M. Rao and B. Nowrouzian
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 311 –314
- DOI: 10.1049/ip-cds:19990725
- Type: Article
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p.
311
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The well known modified Booth recoding technique uses 3-bit overlapped-scanning of two's complement (TC) multipliers for the area-time efficient multiplication of TC numbers. The authors present a novel recoding technique which employs 5-digit overlapped-scanning of signed-binary (SB) multipliers to achieve area–time efficient multiplication of SB numbers. The proposed recoding technique converts SB multipliers into their corresponding modified radix-4 signed-digit (SD) number representation in parallel, leading to two important practical advantages. First, it reduces the number of intermediate partial products formed during the multiplication process by a factor of two. Secondly, it eliminates an otherwise extra addition associated with the formation of each partial product. This elimination is made possible by restricting the recoded multiplier digits to 0, ±1, or ±2, only, effectively eliminating the need for multiplication by ±3. These two features lead to high-speed area-efficient SB multiplication suitable for modern high-performance VLSI and ASIC implementations. - Author(s): K. Galkowski ; E. Rogers ; A. Gramacki ; J. Gramacki ; D.H. Owens
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 315 –320
- DOI: 10.1049/ip-cds:19990726
- Type: Article
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p.
315
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Differential linear repetitive processes are a distinct class of two-dimensional linear systems which can be used, for example, to model industrial processes such as long-wall coal cutting operations. Also, they can be used to study key properties of classes of linear iterative learning schemes. The key feature of interest in the paper is the fact that information propagation in one of the two separate directions in such processes evolves continuously over a finite fixed duration and in the other direction it is, in effect, discrete. The paper develops discrete approximations for the dynamics of these processes and examines the effects of the approximation techniques used on two key systems-related properties. These are stability and the structure of the resulting discrete state-space models. Some ongoing work and areas for further development are also briefly noted. - Author(s): I.S. Kourtev and E.G. Friedman
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 321 –326
- DOI: 10.1049/ip-cds:19990582
- Type: Article
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p.
321
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Designing the topology of a clock distribution network is considered for a synchronous digital integrated circuit so as to satisfy a nonzero clock skew schedule. A methodology and related algorithms for synthesising the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of designing the clock distribution network is given as an efficiently solvable integer linear programming problem. The approach is demonstrated on the suite of ISCAS'89 benchmark circuits. Up to 64% performance improvement is attained on these circuits by exploiting nonzero clock skew throughout the synchronous system. Clock tree topologies that implement the nonzero clock skew schedule based on the synthesis algorithms presented are described for each of the benchmark circuits. - Author(s): J. Lim ; D.-G. Kim ; S.-I. Chae
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 327 –333
- DOI: 10.1049/ip-cds:19990686
- Type: Article
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p.
327
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For ultra-low-energy applications, bootstrapped reversible-energy-recovery logic (bRERL) is proposed, which is a reversible adiabatic CMOS logic and requires an 8-phase clock. In bRERL, each transmission gate was replaced by a bootstrapped nMOS switch in the logic functional blocks of tRERL. Using SPICE simulations, it was confirmed that the bRERL circuit consumed less energy and occupied less area than the tRERL circiut. The authors integrated a bRERL inverter chain with its 8-phase, clocked power generator in a test chip, which was fabricated with 0.6μm CMOS technology. They also confirmed that they could minimize the energy consumption in the bRERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal. - Author(s): C. Yeh and M.-C. Chang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 334 –339
- DOI: 10.1049/ip-cds:19990579
- Type: Article
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p.
334
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The advent of portable and high-density devices has made power consumption a critical design concern. The authors address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. First, a maximum-weighted independent set formulation is used for voltage reduction on the noncritical part of the circuit. Secondly, a minimum-weighted separator set formulation is used to for gate sizing and to integrate the sizing procedure with a voltage scaling procedure to enhance power saving for the whole circuit. The proposed methods are evaluated using the MCNC benchmark circuits. An average of 19.12% power reduction has been achieved over the circuits having only one supply voltage. - Author(s): B.-S. Kong and Y.-H. Jun
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 341 –344
- DOI: 10.1049/ip-cds:19990724
- Type: Article
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p.
341
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A set of novel self-timed latches is introduced and analysed. These latches have no back-to-back connection as in conventional self-timed latches, and both inverting and noninverting outputs are evaluated simultaneously leading to higher operating frequencies. A novel type of cross-coupled inverter used in the proposed circuits implements static operation without the signal fighting with the main driver during signal transition. The power consumption of these latches is also comparable to, or less than, that of conventional circuits. The proposed latches are designed using a 0.35 µm CMOS technology. The comparison results indicate that the proposed active-low self-timed latch (ALSTL) improves speed by 22–34% over the conventional NAND SR latch, while for the active-high self-timed latch (AHSTL) the speed improvements are 20–35% with less power as compared to the corresponding NOR SR latch. - Author(s): A. Schmid ; Y. Leblebici ; D. Mlynek
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 345 –349
- DOI: 10.1049/ip-cds:19990685
- Type: Article
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p.
345
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The authors present a novel artificial-neural-network architecture with on-chip learning capability. The issue of straightforward design-flow integration of an autonomous unit is addressed with a mixed analogue–digital approach, by implementing a charge-based artificial neural network which interacts with digital control and processing units. The circuit architecture and design-flow approach for the case of a Hamming network performing pixel-pattern recognition are described. - Author(s): D.K. Papakostas and A.A. Hatzopoulos
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 350 –354
- DOI: 10.1049/ip-cds:19990581
- Type: Article
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p.
350
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An efficient method for estimating the mean value and standard deviation of output measurements is introduced. It takes into account statistical variations of component values and gives accurate and realistic results with less computational time compared with the Monte Carlo technique. A method for the estimation of fault detectability of output measurements in a simulation-before-test approach is proposed. Results from four different circuits show the effectiveness of the methods in selecting the measurement with the highest detectability among a given set and also their application for input stimulus selection. - Author(s): A. Milne ; D. Taylor ; J. Saunders ; A.D. Talbot
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 146, Issue 6, p. 355 –360
- DOI: 10.1049/ip-cds:19990691
- Type: Article
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p.
355
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The definition of a universally acceptable analogue fault model has been a major obstacle to the acceptance, by industry, of any of the new test and testability techniques that have been proposed for analogue and mixed-signal circuits. This is largely because analogue faults are difficult to model and very time consuming to simulate. Previous independent research has demonstrated how inductive fault analysis can be used to reduce the size of a fault set and how circuit sensitivity analysis can be employed to ascertain what constitutes a fault for each circuit component. The authors combine these two principles by first employing an inductive fault analysis to eliminate faults which are unlikely to occur from the fault set, and then employing a circuit sensitivity analysis to eliminate from the remaining set ‘faults’ which have no effect on circuit functionality. As a result, fault simulation becomes a significantly less onerous task and the evaluation and comparison of test programs and techniques can be achieved much more conveniently.
Electronic noses: a review of signal processing techniques
5-digit overlapped-scanning technique for the modified radix-4 recoding of signed-binary numbers
Higher order discretisation methods for a class of 2-D continuous-discrete linear systems
Synthesis of clock tree topologies to implement nonzero clock skew schedule
Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits
Gate-level voltage scaling for low-power design using multiple supply voltages
Set of self-timed latches for high-speed VLSI
Mixed analogue–digital artificial-neural-network architecture with on-chip learning
Estimation of statistical variables for analogue fault detectability evaluation
Generation of optimised fault lists for simulation of analogue circuits and test programs
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