IEE Proceedings - Circuits, Devices and Systems

Volume 146, Issue 6, December 1999

Volume 146, Issue 6

December 1999

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    • Electronic noses: a review of signal processing techniques
      5-digit overlapped-scanning technique for the modified radix-4 recoding of signed-binary numbers
      Higher order discretisation methods for a class of 2-D continuous-discrete linear systems
      Synthesis of clock tree topologies to implement nonzero clock skew schedule
      Reduction in energy consumption by bootstrapped nMOS switches in reversible adiabatic CMOS circuits
      Gate-level voltage scaling for low-power design using multiple supply voltages
      Set of self-timed latches for high-speed VLSI
      Mixed analogue–digital artificial-neural-network architecture with on-chip learning
      Estimation of statistical variables for analogue fault detectability evaluation
      Generation of optimised fault lists for simulation of analogue circuits and test programs

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