IEE Proceedings - Circuits, Devices and Systems
Volume 144, Issue 6, December 1997
Volumes & issues:
Volume 144, Issue 6
December 1997
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- Author(s): H. Amin ; K.M. Curtis ; B.R. Hayes-Gill
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 313 –317
- DOI: 10.1049/ip-cds:19971587
- Type: Article
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p.
313
–317
(5)
An efficient piecewise linear approximation of a nonlinear function (PLAN) is proposed. This uses a simple digital gate design to perform a direct transformation from X to Y, where X is the input and Y is the approximated sigmoidal output. This PLAN is then used within the outputs of an artificial neural network to perform the nonlinear approximation. The comparison of this technique with two other sigmoidal approximation techniques for digital circuits is presented and the results show that the fast and compact digital circuit proposed produces the closest approximation to the sigmoid function. The hardware implementation of PLAN has been verified by a VHDL simulation with Mentor Graphics running under the UNIX operating system. - Author(s): K.M. Al-Ruwaihi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 318 –322
- DOI: 10.1049/ip-cds:19971401
- Type: Article
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p.
318
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(5)
In on-chip learning feedforward and feedback neural networks, different nonlinear activation functions are required. To date, these different functions are realised by physically changing the activation circuits. A novel CMOS analogue circuit suitable for modelling neurons with programmable activation functions is introduced. The proposed circuit is realised by optimising the second-order components of MOS transistors. Programmability of the activation function is achieved using an external controlling signal. Intensive simulations based on SPICE3 indicate that the proposed circuit can realise different activation functions including step, linear threshold, and sigmoid functions. - Author(s): D.J. Soudris ; V. Paliouras ; T. Stouraitis ; A. Thanailakis
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 323 –328
- DOI: 10.1049/ip-cds:19971548
- Type: Article
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p.
323
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(6)
A systematic methodology for the parallel implementation of the multidimensional circular convolution algorithm is introduced. The methodology can be applied when at least one of the convolved sequences is separable. The multidimensional algorithm is described hierarchically by two levels of two-dimensional directed graphs. The top level corresponds to a graph, each node of which represents a one-dimensional convolution, while the lower level graph specifies the elementary operations within the one-dimensional algorithm. The array architectures result systematically from the application of novel partitioning and scheduling techniques onto the top-level graph. Depending on the proposed partitioning strategy, highly-pipelined architectures with either serial or parallel loading of data can be derived. - Author(s): A.G.M. Strollo and E. Napoli
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 329 –334
- DOI: 10.1049/ip-cds:19971487
- Type: Article
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p.
329
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(6)
An improved version of a recently proposed PIN diode circuit model is proposed. The most appealing feature of this model is the easy parameter extraction procedure, that requires neither an in-depth knowledge of device manufacturing, nor particularly complex measurements of device characteristics. The parameter extraction procedure developed in the paper is carried out in an automatic fashion, with the help of a new stochastic global optimisation algorithm. A comprehensive set of experimental results shows the effectiveness of the PIN diode model and of the parameter extraction technique. - Author(s): A. Mahmood ; Y. Chu ; T. Sobh
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 335 –342
- DOI: 10.1049/ip-cds:19971566
- Type: Article
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p.
335
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Sparse-matrix solution is a dominant part of execution time in simulating VLSI circuits by a detailed simulation program such as SPICE. The paper develops a parallel-block partitionable sparse-matrix-solution algorithm which exploits sparsity at the matrix block level as well as within a nonzero block. An efficient mapping scheme to assign different matrix blocks to processors is developed which maximises concurrency and minimises communication between processors. Associated reordering and efficient sparse storage schemes are also developed. Implementation of this parallel algorithm is carried out on a transputer processor array which plugs into a PC bus. The sparse matrix solver is tested on matrices generated from a transistor-level expansion of ISCAS-85 benchmark logic circuits. Good acceleration is obtained for all benchmark matrices up to the number of transputers available. - Author(s): J. Tsimbinos and K.V. Lever
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 343 –349
- DOI: 10.1049/ip-cds:19971589
- Type: Article
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p.
343
–349
(7)
Previous work has shown that phase-plane and state-space error tables can be used to improve the linearity of analogue-to-digital converters. The calibration signals used to generate the error table were incremented amplitude sinusoids, leaving unfilled regions in the table that correspond to the high input signal frequencies and amplitude levels, and usually highest error. The paper proposes the use of more elaborate calibration signals for generating the error tables. It is shown that the use of pseudorandom calibration signals leads to superior error-table coverage and improved compensation over the frequency range of interest. The error-table compensation method is briefly compared with an alternative technique based on the Volterra inverse. - Author(s): G.A. Ruiz
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 350 –354
- DOI: 10.1049/ip-cds:19971445
- Type: Article
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p.
350
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(5)
The paper presents new compact static 4-bit CMOS adders based on iterative shared transistor carry lookahead (CLA) units. The CLA units have a regular, fast, simple and multi-output static structure with a small number of transistors. Designs made in 1.0 µm CMOS technology show that these adders reduce the silicon area and improve the timing and dynamic power performance compared with similar static adders. - Author(s): H. Kim ; I.S. Choi ; S.Y. Hwang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 355 –360
- DOI: 10.1049/ip-cds:19971481
- Type: Article
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p.
355
–360
(6)
A pair of heuristic algorithms based on Shannon expansion are proposed for the synthesis of low-power combinational circuits. Selecting an input variable for a given function, the bipartitioning algorithm performs Shannon expansion with respect to a selected variable to reduce the power dissipation of the subcircuit implementing the cofactor. The multiple partitioning algorithm partitions a given circuit into several subcircuits such that only a subcircuit can be activated at a time to reduce unnecessary signal transitions. In the algorithm, a circuit is recursively partitioned by applying Shannon expansion as long as power consumption is reduced. Experimental results for the MCNC benchmarks show that the bipartitioning and multiple partitioning algorithms based on Shannon expansion are effective by generating circuits consuming 39.1 and 50.5% less power on the average, respectively, when compared to the conventional algorithm based on precomputation logic. - Author(s): J.L. González and A. Rubio
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 361 –366
- DOI: 10.1049/ip-cds:19971551
- Type: Article
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p.
361
–366
(6)
Several low noise logic schemes for mixed mode integrated circuit design have been presented over the last few years. These logic approaches are used to diminish the level of switching noise generated by the digital part of the circuit. In the paper the testability of one of these approaches is analysed: folded source-coupled logic (FSCL). A basic FSCL inverter with two kind of realistic fault (bridge and open circuit, including floating gates) is simulated. The effects of the realistic faults in various observable magnitudes are presented and discussed, and some test approaches are suggested. - Author(s): T.-H. Kuo ; S.-Y. Lee ; D.-J. Lu ; T. Jih ; J.-J. Tsaur
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 367 –374
- DOI: 10.1049/ip-cds:19971588
- Type: Article
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p.
367
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A low-cost, low-voltage, mixed-mode integrated circuit for speech applications is presented. The mixed-mode IC can directly preamplify speech signals with the aid of automatic gain control, convert amplified signals to 1-bit digital codes at 24 kbit/s, store the converted codes in memory, and replay the stored codes through an on-chip current-input voltage-output power amplifier. Switched-current techniques are used to implement a filter with a 3.4 kHz bandwidth and a 96 kHz sampling frequency, and also an adaptive delta modulator (ADM) with a 24 kHz sampling frequency. Measured dynamic range of the SI ADM combined with the SI filter is greater than 40 dB. This mixed-mode IC, operating with a 3.3 V supply voltage, was fabricated by a 1.5-µm single-poly single-metal CMOS process. The whole system has been tested using human voice and results show that it is highly suitable for low-cost speech applications. - Author(s): Y. Zebda ; A. Elnagar ; A. Hussein
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 375 –377
- DOI: 10.1049/ip-cds:19971488
- Type: Article
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p.
375
–377
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A new trial function for the base doping profile in AlGaAs/GaAs heterojunction bipolar transistor (HBT) is proposed. It is found that for certain doping parameters this base doping profile will minimise the base transit time. Furthermore, this function is neither exponential nor Gaussian as claimed by previous studies. In the paper the base width and the peak base doping are held constant. - Author(s): ChulwooKim and SoowonKim
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 6, p. 378 –380
- DOI: 10.1049/ip-cds:19971288
- Type: Article
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p.
378
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A modified MOS REL structure, which explores the wired-OR property and enhances speed and power characteristics, is proposed. Proposed MOS REL gates have been fabricated and tested. It is shown that the power × delay of the MOS REL inverter is enhanced by 26% with less silicon area.
Piecewise linear approximation applied to nonlinear function of a neural network
CMOS analogue neurone circuit with programmable activation functions utilising MOS transistors with optimised process/device parameters
Design methodology for the implementation of multidimensional circular convolution
Improved PIN diode circuit model with automatic parameter extraction technique
Parallel sparse-matrix solution for direct circuit simulation on a transputer array
Improved error-table compensation of A/D converters
New static multi-output carry lookahead CMOS adders
Design of heuristic algorithms based on Shannon expansion for low-power logic circuit synthesis
Testability aspects of folded source-coupled logic
3.3 V mixed-mode IC design using switched-current techniques for speech applications
Minimisation of base transit time in AlGaAs/GaAs heterostructure bipolar transistor (HBT)
Wired-OR property and improved structure of recovered energy logic (REL)
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