IEE Proceedings - Circuits, Devices and Systems
Volume 144, Issue 3, June 1997
Volumes & issues:
Volume 144, Issue 3
June 1997
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- Author(s): J.-S. Ker ; Y.-H. Kuo ; B.-D. Liu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 129 –137
- DOI: 10.1049/ip-cds:19971005
- Type: Article
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p.
129
–137
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The primary advantages of a CMAC neural network are fast learning and insensitivity to the order in which training patterns are presented. The authors present an extended direct weight cell address mapping mechanism based on a linear systolic array architecture to realise a higher-order CMAC neural network with digital hardware. This higher-order CMAC implementation has been applied to calibrate and compensate the nonlinearity of chromatic mapping between colour scanning and printing devices in a colour image reproduction environment. A 20 MHz prototyped CMAC chip for colour calibration has been implemented to confirm the proposed design approach. Using this prototype, the authors were able to achieve reproduced colour images with rich and vivid colours which strongly resemble the original. - Author(s): T.-S. Chang and C.-W. Jen
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 138 –144
- DOI: 10.1049/ip-cds:19971009
- Type: Article
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p.
138
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Two embedded memory designs are proposed for video-signal processing. Concurrent line access performs multiple-port memory accesses at the hardware cost and access time of a single port. It uses 62.24% of the area required by a conventional dual-port memory and is only 7.6% larger than a single-port 2 K × 8 memory. The block-access mode combines address decoders and generators, yielding block-access mode times 26% faster than conventional schemes for a 256 words × 32 bits memory size. Despite some preferred-access-order restrictions, the designs incur no loss of generality because video algorithms possess high data parallelism and low dependence. - Author(s): T.S. Dranger and R. Priemer
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 145 –148
- DOI: 10.1049/ip-cds:19971148
- Type: Article
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p.
145
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Comparing and sorting are common functions in natural and artificial systems. Many known algorithms that sort m numbers require time from O(m2) to O(m). Algorithms to find the greatest number have been realised in neural networks and discrete time systems. Presented in the paper is a new circuit, the MAXOR, which incorporates a continuous time recursive collective process for finding the maximum of many inputs and sort inputs, like the O(m) spaghetti sort algorithm, when furnished with synchronous control. The resulting output is broadcast throughout the process. The precision η required of the circuit is only that needed to distinguish between the maximum and next lower inputs. Stability is assured within practical parameters where the output is observed to settle in linearised time O(m/η). - Author(s): Y. Maidon ; B.W. Jervis ; N. Dutton ; S. Lesage
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 149 –154
- DOI: 10.1049/ip-cds:19971146
- Type: Article
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p.
149
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It is shown, by means of an example, how multiple faults in bipolar analogue integrated circuits can be diagnosed, and their resistances determined, from the magnitudes of the Fourier harmonics in the spectrum of the circuit responses to a sinusoidal input test signal using a two-stage multilayer perceptron (MLP) artificial neural network arrangement to classify the responses to the corresponding fault. A sensitivity analysis is performed to identify those harmonic amplitudes which are most sensitive to the faults, and also to which faults the functioning of the circuit under test is most sensitive. The experimental and simulation procedures are described. The procedures adopted for data preprocessing and for training the MLPs are given. One hundred percent diagnostic accuracy was achieved, and most resistances were determined with tolerable accuracy. - Author(s): A.J. van de Goor and G.N. Gaydadjiev
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 155 –160
- DOI: 10.1049/ip-cds:19971147
- Type: Article
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p.
155
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Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts; a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests. - Author(s): J. Rodriguez Tellez ; E. Diaz Asua ; D. Ariñez
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 161 –166
- DOI: 10.1049/ip-cds:19971079
- Type: Article
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p.
161
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The active inductors proposed by Zhang, Hara, Khoury and Kaunisto are assessed for their suitability for microwave filtering applications. Versions of these circuits utilising a cascode arrangement as a means of improving the resistance of the circuits are also considered. The assessment considers such issues as inductance, resistance, frequency range, power consumption and device requirements. - Author(s): S.-J. Jou ; M.-F. Perng ; C.C. Su
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 167 –177
- DOI: 10.1049/ip-cds:19970871
- Type: Article
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p.
167
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A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced. - Author(s): C.A. Papazoglou and C.A. Karybakas
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 178 –184
- DOI: 10.1049/ip-cds:19971078
- Type: Article
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p.
178
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A complete state variable biquadratic filter built by CCIIs with variable current gain is presented and analysed. All the coefficients of the filter can be independently tuned through the variable current gain factors of the current conveyors. The authors propose fundamental techniques for the circuit implementation of the filter from the state variable block diagram. Design criteria to minimise the influence of the current conveyors' parasitic elements on the filter performance are presented. Based on the principles upon which the general biquadratic filter was constructed, a universal filter is proposed which implements the low-pass, high-pass, band-pass, band-reject and all-pass second order transfer functions simultaneously. Experimental measurements using Senani's current conveyor as well as PSPICE simulation using Surakampontorn's CCII were very close to theoretical values. - Author(s): M.M. Al-Ibrahim and A.M. Al-Khateeb
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 185 –189
- DOI: 10.1049/ip-cds:19971004
- Type: Article
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p.
185
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An extremely low-frequency digital sinusoidal oscillator is proposed and its performance is evaluated. The proposed oscillator structure can generate sinusoidal signals with a large number of samples per cycle without the need for increasing the width of the multiplier coefficient. The difference between two adjacent generated frequencies is shown to be approximately constant over the frequency range of operation. The proposed oscillator utilises one multiple-output direct-form digital oscillator together with very simple shift operations. Simulation results are given to verify the analysis and demonstrate the performance as measured in terms of total harmonic distortion. - Author(s): V. Moshnyaga ; Y. Mori ; H. Onodera ; K. Tamaru
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 190 –194
- DOI: 10.1049/ip-cds:19970643
- Type: Article
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p.
190
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The authors present a tool for generating a performance-driven placement from a netlist of register-transfer level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks in such a way as to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that the tool provides solutions close to those generated manually, is fast enough to be used in the inner loop of a program which synthesises RTL structures from behavioural specifications and ensures the strong links between RTL synthesis and timing-driven layout which are so necessary for design of submicron ASICs. - Author(s): H.O. Elwan and A.M. Soliman
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 144, Issue 3, p. 195 –200
- DOI: 10.1049/ip-cds:19971081
- Type: Article
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p.
195
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Novel CMOS realisations of a differential voltage current conveyor (DVCC) are described. These circuits are powerful building blocks, especially for applications demanding differential or floating inputs like impedance converter circuits and current mode instrumentation amplifiers. Applications suitable for VLSI are then considered by using the DVCC to realise a MOS transconductor and a continuous-time current mode MOSFET-C filter. PSpice simulations indicate the excellent performance of the proposed DVCC and of its circuit applications.
Systolic implementation of higher-order CMAC and its application in colour calibration
On-chip memory module designs for video-signal processing
Collective process circuit that sorts
Diagnosis of multifaults in analogue circuits using multilayer perceptrons
March U: a test for unlinked memory faults
Assessment of active microwave inductors
Hierarchical techniques for symbolic analysis of electronic circuits
Noninteracting electronically tunable CCII-based current-mode biquadratic filters
Digital sinusoidal oscillator with low and uniform frequency spacing
Performance-driven macro-block placer for architectural evaluation of ASIC designs
Novel CMOS differential voltage current conveyor and its applications
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