IEE Proceedings - Circuits, Devices and Systems
Volume 143, Issue 1, February 1996
Volumes & issues:
Volume 143, Issue 1
February 1996
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- Author(s): F. Güneş ; F. Gurgen ; H. Torpi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 1 –8
- DOI: 10.1049/ip-cds:19960150
- Type: Article
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A new method for concurrently modelling the small-signal and the noise performance of active microwave devices is proposed. Here, the device is modelled by a black box whose small signal and noise parameters are evaluated through a neural network, based upon the fitting of both of these parameters over the operational bandwidth of the device. On using the concurrent modelling procedure, it has been found that, not only can the small-signal performance be simulated accurately, but also the prediction of noise performance is in much better agreement with measurements than those of recent published models. - Author(s): S. Johnson and M.J. Morant
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 9 –13
- DOI: 10.1049/ip-cds:19960034
- Type: Article
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The authors describe a mechanism which allows CMOS circuits containing a break in a power supply track (referred to as open circuit supply faults) to operate with little change in their performance parameters. In circuits containing such faults, current can be supplied through the substrate or well contacts enabling logic gates to operate at full design speed. Measurements on circuits containing such faults and results of simulations are presented to demonstrate the effect of the fault. The circuits operate normally, although they may be susceptible to latch-up behaviour and may fail in this way. Transient latch-up testing is recommended to detect such faults. - Author(s): A.S. Ashur ; M.K. Ibrahim ; A. Aggoun
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 14 –20
- DOI: 10.1049/ip-cds:19960171
- Type: Article
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14
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A new architecture for digit-serial multiplication is presented. The new digit-serial multiplier is the first reported systolic design where the delay in obtaining the least significant digit (i.e. the initial delay) is independent of the number of digits and hence the wordlength. Although the new architecture has a bidirectional data flow, all the cells are used with 100% efficiency. This is achieved by combining, in a novel way, the operation of two basic cells used in the conventional structures. The proposed multiplier is the ideal design to use in DSP structures that have data feedback paths such as IIR filters, because it has localised communications and has the lowest possible latency as well as being modular and regular. The new structure also allows a high level of pipelining to increase the throughput rate. The performance and the effect of pipelining levels on the throughput rate and hardware cost for the new structure is also presented to allow designers to find the best tradeoff between hardware cost and multiplication time. - Author(s): A.D. Brown ; K.G. Nichols ; M. Zwolinski
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 21 –27
- DOI: 10.1049/ip-cds:19960013
- Type: Article
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21
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A unique method of using inertial cancellation in the detection of set-up and hold-time violations in flip-flops and other memory-like elements is described, together with an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques. - Author(s): J. Zeng ; P.A. Mawby ; M.S. Towers ; K. Board
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 28 –32
- DOI: 10.1049/ip-cds:19960146
- Type: Article
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The quasisaturation behaviour in the high voltage MOSFET structure with a vertical trench gate (UMOS) is studied and demonstrated using 2D numerical simulation techniques. The results show that the quasisaturation effect is mainly due to the conduction area and conductance of the drift region becoming the main constraint at high gate voltage and drain current levels. A simple analytical expression for the quasisaturation current using a simple resistive model is derived and verified based on the simulation results. The effect that the geometry of the trench has on the quasisaturation behaviour is studied, and it is found that increasing the depth and width of the trench improves the quasisaturation operation. - Author(s): G. Verzellesi ; A. Dal Fabbro ; P. Pavan ; L. Vendrame ; E. Zabotto ; A. Zanini ; A. Chantre ; E. Zanoni
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 33 –40
- DOI: 10.1049/ip-cds:19960144
- Type: Article
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A nonlocal, energy based impact ionisation model for bipolar transistors is implemented into a general purpose circuit simulator. With respect to conventional, either empirical or electric field based, models, the proposed approach enables a more physical and accurate description of impact ionisation effects in modern, high speed bipolar transistors, where non-negligible nonstationary transport effects take place as a consequence of the strong spatial variations in the electric field at the base–collector junction. The conventional base resistance model is also modified, to take into account the base resistance dependence on bias in the presence of an impact ionisation induced reverse base current. Neglecting the influence of the reverse base current on the base resistance can result in an underestimation of the degradation of both DC and switching performance of bipolar transistors due to impact ionisation. The implemented models are validated by comparison with experimental results obtained from devices of two different technologies. - Author(s): Y.K. Seng and S.S. Rofail
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 41 –45
- DOI: 10.1049/ip-cds:19960147
- Type: Article
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41
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A new generation of noncomplementary BiCMOS digital gates for low-voltage, low-power applications is presented. These include an inverter and a NAND gate. A bootstrapping technique is employed in the pull-up and pull-down cycles to give high speed and a rail-to-rail operation. The performance evaluation has shown that the new circuits outperform the CMOS and the recently reported circuits in terms of speed, output voltage swing, power-delay product and maximum operating frequency. The crossover capacitance of the new circuit has been shown to be 50 per cent lower than the B2CMOS. A transient model for the basic circuit configuration is developed to relate the key device parameters to the pull-up response, and HSPICE simulations have been used to characterise the circuits. The experimental results have also verified the operation of the proposed circuit. - Author(s): M.O. Hawksford
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 46 –52
- DOI: 10.1049/ip-cds:19960149
- Type: Article
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An amplifier topology is introduced that functions principally in a current-steering mode and offers wide bandwidth and low distortion. The cell can accommodate an additional difference port and thus finds application in a range of audio amplifier incorporating error correction. The cell topology and its properties are described and methods of error correction are reviewed where it is shown that the new topology can be used in both single-ended and balanced power amplifiers. - Author(s): H.-T. Sheu and Y.-H. Chang
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 53 –60
- DOI: 10.1049/ip-cds:19960151
- Type: Article
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p.
53
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A hierarchical frequency-domain robust component failure detection (RCFD) scheme is proposed for the robust fault diagnosis of large-scale analogue circuits with both component tolerances and measurement errors. In the proposed scheme, robust detection filters designed by using the full-rank measurement for each hierarchy of the stratified circuit are employed to generate the robust residuals for fault isolation (FI), and the effect of both component tolerances and measurement errors to the diagnostic result is reduced by using the carefully evaluated residual thresholds, and the RCFD is achieved. In the paper, the design of the robust detection filters and the evaluation of the residual thresholds are presented and a circuit-hierarchical full-rank measurement condition is proposed. A large-scale analogue circuit is illustrated. The results indicate that, without any a priori information about the type of component failure, precise diagnosis for a large-scale circuit with both component tolerances and measurement errors is accomplished at low measurement cost. - Author(s): R.G. Villanueva and H.J. Aguilar
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 61 –67
- DOI: 10.1049/ip-cds:19960093
- Type: Article
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p.
61
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The paper presents three new amplifier circuits that use a special type of linear negative feedback to efficiently compensate their nonlinearities. The Volterra transfer functions of each amplifier were found by means of a structural method analysis of weakly nonlinear systems, based on the joint application of the Volterra–Wiener theory for nonlinear systems and the structural theory for linear ones. The necessary conditions for optimising the linear behaviour of the special feedback amplifiers were obtained. With these conditions, the amplifiers only compensate second- and third-order nonlinearities, meanwhile the linear gains do not suffer the typical reduction caused by the conventional feedback. In addition, experimental realisations of the high linearity amplifiers were tested to validate theoretical results and demonstrate the practical importance of these new structures in some applications. - Author(s): F.J. García Sánchez ; A. Ortiz–Conde ; J.J. Liou
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 68 –70
- DOI: 10.1049/ip-cds:19960159
- Type: Article
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p.
68
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A new method is presented that permits the extraction of a semiconductor device's intrinsic model parameters from its experimental extrinsic forward I–V characteristics, independently of the parasitic resistance that might be present in series within the real device. The extraction is performed from an auxiliary function which contains the integral of the experimentally measured data. Integrating the data also serves as a smoothing procedure. The diode quality factor, reverse current and series resistance parameters of a single exponential diode model are extracted from a real p-n junction diode in order to illustrate the method. - Author(s): R. Senani and V.K. Singh
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 143, Issue 1, p. 71 –72
- DOI: 10.1049/ip-cds:19960015
- Type: Article
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p.
71
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Signal–noise neural network model for active microwave devices
Nonstuck behaviour of open circuit supply faults in CMOS logic circuits
Systolic digit-serial multiplier
Issues in the design of a logic simulator: element modelling for efficiency
Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate
SPICE modelling of impact ionisation effects in silicon bipolar transistors
1.1 V full-swing double bootstrapped BiCMOS logic gates
Quad-input current-mode asymmetric cell (CMAC) with error correction applications in single-ended and balanced audio amplifiers
Hierarchical frequency-domain robust component failure detection scheme for large-scale analogue circuits with component tolerances
Amplifier linearisation through the use of special negative linear feedback
Parasitic series resistance-independent method for device-model parameter extraction
Comment: Synthesis of canonic single-resistance-controlled-oscillators using a single current-feedback-amplifier
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