IEE Proceedings - Circuits, Devices and Systems
Volume 142, Issue 3, June 1995
Volumes & issues:
Volume 142, Issue 3
June 1995
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- Author(s): J. Raczkowycz and S. Allott
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 145 –152
- DOI: 10.1049/ip-cds:19951926
- Type: Article
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145
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A novel data analysis technique for testing embedded ADCs known as data optimisation is presented that alleviates scan-path loading and, when used as part of a go/no-go test, reduces the amount of primary of primary-test data and computer-time intensive operations to a minimum. To implement this test technique, a BIST scheme is presented which increases the control and observation of an embedded ADC, and enables real-time testing of an embedded 8-bit ADC with a 78% reduction in the amount of data needed to be shifted off-chip. Finally, comparisons between theoretical, modelled and practical results are made and appropriate conclusions drawn. - Author(s): I. Andreadis ; P. Iliades ; Y. Karafyllidis ; P. Tsalides ; A. Thanailakis
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 153 –157
- DOI: 10.1049/ip-cds:19951891
- Type: Article
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p.
153
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The design and VLSI implementation of a new ASIC, which performs the conversion, in real time, of the R, G and B colour co-ordinates to the CIE standard L*, a* and b* colour coordinates, are presented. The rate of operation of this ASIC is 106.4 MIPS. The high-speed operation is achieved by pipelining the data in a vector fashion. The ASIC is implemented using a DLM, 1.0 µm, N-well, CMOS process provided by European Silicon Structures (ES2), and it occupies a silicon area of 6.30*6.45 mm=40.63 mm2. It is intended to be used in colorimetry instrumentation for colour measurement and control and in colour machine vision in autonomous applications such as robotics and military systems, where the need for short processing times is crucial. - Author(s): Y. Chen ; W.K. Tsai ; F.J. Kurdahi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 158 –164
- DOI: 10.1049/ip-cds:19951925
- Type: Article
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p.
158
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In a system level or logic level design process, the decisions made during early phases of the high level design have the greatest impacts on the performance of the final chip. However, these impacts will not be realised until very late in the physical design stage. In addition, it has been observed repeatedly that the most frustrating problem in IC design is to understand the relationship between the early phase decisions and the final layout result. It is therefore important, in logic synthesis to optimise a cost function which could relate the logic equation and the final layout performance. The authors develop a logic synthesis approach which relies on an accurate design evaluation program to estimate the final design attributes such as layout area and speed. Given a candidate design implementation, an evaluation program will be called upon to provide quick and accurate estimates of the layout area or critical path delay. This information will then be used as a feedback to the logic optimisation system. Based on this feedback, the system will 'reorient' itself toward a new direction for optimisation. Such a scheme represents a more realistic way of generating optimal layout implementations. - Author(s): T. Hanyu ; S. Aragaki ; T. Higuchi
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 165 –172
- DOI: 10.1049/ip-cds:19951949
- Type: Article
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165
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A design of a high-density multiple-valued content-addressable memory (MVCAM) is presented. The key concept of the proposed MVCAM is a functionally separated configuration in which the cell functions are split into two basic parts: a threshold function and logic-value conversion. Complicated search operations are synthesised by the combination of these two basic functions. The circuit for logic-value conversion is designed by a binary-to-multiple-valued encoder as a peripheral circuit. Input data are encoded by the logic-value conversion and are distributed to each CAM cell. A CAM cell for performing the threshold function is simply designed using one floating-gate MOS transistor. Separating the complex search operations into the threshold function and the logic-value conversion, a simple CAM cell can be achieved. As a result, it is estimated that a 1 Mbit four-valued CAM can be implemented using conventional flash EEPROM technologies and is useful in two typical applications. - Author(s): S. Pammu and S.F. Quigley
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 173 –178
- DOI: 10.1049/ip-cds:19951927
- Type: Article
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p.
173
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An analogue CMOS circuit technique for the implementation of defuzzification is proposed. The defuzzification method is based upon the normalisation locked loop (NLL) method, but with two key improvements: the compact representation of triangular membership functions, and a mechanism to ensure that the relative rule weight proportions are preserved during normalisation. Circuit complexity is considerably reduced by combining these two operations in a single circuit stage. The proposed weight circuit, which evaluates normalised rule weights, has been realised using current squaring circuits proposed by Bult and Wallinga (1987). The weight circuit has been fabricated in a 2.0 µm CMOS process. Results obtained from the fabricated circuit operating as part of a NLL are presented. - Author(s): R.F. Woods ; G. Floyd ; K. Wood ; R. Evans ; J.V. McCanny
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 179 –185
- DOI: 10.1049/ip-cds:19951892
- Type: Article
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p.
179
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The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described. - Author(s): J.-J. Chen ; H.-W. Tsao ; S.-I. Liu ; W. Chiu
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 186 –192
- DOI: 10.1049/ip-cds:19951950
- Type: Article
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p.
186
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A parasitic-capacitance-insensitive MOSFET-C integrator and differentiator using operational transresistance amplifiers are proposed and experimental results demonstrated. The bandwidths of these circuits are also independent of their gains. The required capacitances are smaller than those in previous work. Two new configurations of universal current-mode biquad filters based on these circuits are presented. A second-order bandpass filter constructed using universal biquad filters and another third-order Chebyshev lowpass filter with 0.1 dB passband ripple are breadboarded and the measured results presented. - Author(s): A. Tawfik ; F. El-Guibaly ; P. Agathoklis
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 193 –199
- DOI: 10.1049/ip-cds:19951946
- Type: Article
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p.
193
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An efficient (in the area*time sense) systolic implementation for Nth-order state-space IIR digital filters is presented. The number of processor elements involved in the implementation is linear with respect to the filter order. All double-precision operations are localised inside the processor units and efficiently executed using novel high-speed inner-product processors. The paths between the processor elements carry single-precision data which results in reducing the communication overhead. These features combine to improve area*time performance measure without any increase in the output roundoff noise. The proposed architecture renders the state-space structures of IIR digital filter more amendable to hardware implementations. A comparison in terms of computation delay and hardware area between the suggested architecture and non-systolic parallel architecture is presented. This comparison shows that the proposed implementation provides a better performance in the area*time sense over the fully parallel architecture. - Author(s): I. Batarseh
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 200 –204
- DOI: 10.1049/ip-cds:19951890
- Type: Article
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p.
200
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Generalised state-plane analysis for a half-bridge parallel resonant converter (PRC) operating in continuous conduction mode is presented. It is shown that a PRC circuit of any order can be analysed in terms of simple two-dimensional state-plane diagrams, without having to use any sinusoidal approximation. The approach presented makes use of the state-variable transformation technique previously used for the analysis of second- and third-order resonant converters. This method is applied to a specific example of a sixth-order parallel resonant converter operated in the continuous conduction mode. - Author(s): J. Zeng ; P.A. Mawby ; M.S. Towers ; K. Board
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, p. 205 –207
- DOI: 10.1049/ip-cds:19951952
- Type: Article
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p.
205
–207
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The effect of different carrier lifetimes on the forward I-V characteristics of a MOS-controlled thyristor (MCT) has been studied using numerical simulation. Those physical mechanisms that have a strong effect on the forward operation of the MCT have been identified and taken into account. The results show that in the design tradeoff between the switching speed and forward current capability there exists a characteristic lifetime below which the operation mode changes from thyristor-like to IGBT-like, and in the transfer between them a region of differential negative resistance exists. - Author(s): R. Senani
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 142, Issue 3, page: 208 –208
- DOI: 10.1049/ip-cds:19951944
- Type: Article
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p.
208
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Introduces a new configuration that possesses the novel feature of realising positive as well as negative linear VCZs from the same structure by the simple artifice of changing only one interconnection, and hence can be called a universal VCZ configuration. Two different and separate structures for realising positive and negative linear VCZs are no longer required. The proposed configuration not only employs fewer components than previously reported VCZ structures but also is functionally more versatile than all of them.
Embedded ADC characterisation techniques
Design and VLSI implementation of a new ASIC for colour measurement
Layout driven logic synthesis system
Functionally separated, multiple-valued content-addressable memory and its applications
Novel analogue CMOS defuzzification circuit
Programmable high-performance IIR filter chip
Parasitic-capacitance-insensitive current-mode filters using operational transresistance amplifiers
Systolic implementation of fixed-point state-space digital filter
State-plane approach for the analysis of half-bridge parallel resonant converters
Effect of carrier lifetimes on forward characteristics of MOS-controlled thyristors
Universal linear voltage-controlled-impedance configuration
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