IEE Proceedings - Circuits, Devices and Systems
Volume 141, Issue 1, February 1994
Volumes & issues:
Volume 141, Issue 1
February 1994
Editorial
- Author(s): D. Olver and P. Grant
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, page: 1 –1
- DOI: 10.1049/ip-cds:19942402
- Type: Article
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Editorial: Polysilicon devices and applications
- Author(s): M.J. Powell
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, page: 2 –2
- DOI: 10.1049/ip-cds:19942403
- Type: Article
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- Author(s): M.G. Clark
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 3 –8
- DOI: 10.1049/ip-cds:19949953
- Type: Article
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Thin-film polysilicon insulated-gate field effect transistors deposited on glass substrates are the subject of worldwide research and development activity. The greatest motivation for this is their application to flat-panel displays, including, in particular, active-matrix liquid crystal displays (AMLCDs), where they offer several important advantages over the more mature amorphous silicon thin-film transistor (TFT) technology. One of these is the ready availability of both n-type and p-type poly-Si TFTs. Polysilicon-on-glass CMOS TFT technology may be used to fabricate AMLCD drivers on the display substrate; it can also be used in a variety of other applications such as printers, scanners, smart sensors and neural networks. This review identifies the major achievements and key issues in the development of poly-Si TFT technology for both display and nondisplay applications. - Author(s): R.J. Stroh ; F. Plais ; T. Kretz ; P. Legagneux ; O. Huet ; M. Magis ; D. Pribat ; N. Jiang ; M.C. Hugon ; B. Agius
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 9 –13
- DOI: 10.1049/ip-cds:19949949
- Type: Article
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Polycrystalline silicon is a promising candidate for the fabrication of thin-film transistors used to control the pixel voltage of active-matrix liquid-crystal displays. Results are presented on the ultra-high vacuum chemical vapour deposition of silicon thin films and on the gate-oxide deposition at low temperature by distributed electron-cyclotron-resonance-plasma-enhanced chemical vapour deposition. It is shown that high electron mobilities and low off currents characterise the transistors fabricated with these techniques. - Author(s): T.E. Dyer ; J.M. Marshall ; W. Pickin ; A.R. Hepburn ; .F. Davies
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 15 –18
- DOI: 10.1049/ip-cds:19949959
- Type: Article
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The authors report on the optoelectronic and structural properties of polysilicon produced by excimer (ArF) laser crystallisation of undoped hydrogenated amorphous silicon (a-Si:H). Micro-structure and average grain size are determined by TEM and electron diffraction. A maximum areal grain size of 0.2 µm2 is observed in excimer (ArF) laser crystallised polysilicon, grain size is also demonstrated to be dependent on the a-Si:H precursor deposition temperature. UV reflectivity and FTIR spectroscopy are employed to investigate the degree of crystallinity and atomic bonding configurations. DC conductivity measurements are used to infer information on transport properties. These data are compared with studies of low-temperature (600 degrees C) furnace crystallised polysilicon. - Author(s): M. Sarret ; A. Liba ; O. Bonnaud ; F. Le Bihan ; B. Fortin ; L. Pichon ; F. Raoult
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 19 –22
- DOI: 10.1049/ip-cds:19949827
- Type: Article
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Polysilicon devices on glass substrates for large-area applications, such as poly-Si thin-film transistors in active-matrix displays, need a complete low-temperature process, especially to fabricate the drain and source polysilicon layers as well as the active channel layer. For this purpose, we have developed a very low pressure chemical vapour deposition process allowing in-situ phosphorous doping. By varying total pressure and phosphine/silane ratio, we control the doping concentration level over a large range (1018 to 5*1020 cm-3). Depending on deposition conditions, films are first amorphous or partially crystallised. The films are then fully crystallised by a 12 h in-situ vacuum annealing at 600 degrees C. They are physically and electrically characterised. It is observed that in the 30 to 90 pascal pressure range, the dopant activation rate, electrical carrier mobility, and conductivity of the layers are optimised whatever the doping level. First runs of low temperature processed TFTs involving in-situ highly doped source and drain layers have given promising results. - Author(s): Y. Wu ; J.H. Montgomery ; A. Refsum ; S.J.N. Mitchell ; B.M. Armstrong ; H.S. Gamble
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 23 –26
- DOI: 10.1049/ip-cds:19949826
- Type: Article
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Solid-state diffusion and conventional ion implantation are not suitable for source and drain regions formation of polysilicon thin-film transistors on glass substrates. A 30 cm diameter large-area low-energy ion shower implanter with RIPE ion source and double-grid extraction system was developed as a possible low-cost solution. The ion beam current density for hydrogen plasma was 100 µA/cm2 for 3 keV implant energy, 300 W RF power, 140 gauss magnetic field and 3*10-4 mbar pressure. The uniformity of beam current density over the central 20 cm diameter was ±3.5%. Phosphorus implantation has been performed using a 15% PH3 in H2 gas mixture. Implantation at 3 keV for 5 min. results in an integrated dose of 2.48*1016 cm-2 with the concentration peak at a depth of 8.3 nm. Planar and mesa diodes fabricated on p-type silicon substrates have yielded fine rectifier characteristics. The shower implanter is thus suitable for TFTs source and drain region formation. - Author(s): J.R. Ayres ; S.D. Brotherton ; I.R. Clarence ; P.J. Dobson
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 27 –32
- DOI: 10.1049/ip-cds:19949952
- Type: Article
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Steady-state photocurrents have been measured in poly-Si TFTs fabricated from columnar poly-Si as well as from material crystallised from amorphous LPCVD and PECVD precursors. With top face white light illumination, through the poly-Si gate, the photocurrents from all three technologies were comparable and showed similar trends of increasing photocurrent with film thickness. The photocurrents measured in the thinnest films (600 AA thick) were approximately 7*10-14 A/ µm of channel width/klux. With back face illumination the currents were approximately four times larger. When compared with dark current values of approximately 4*10-14 A/ µm in high quality TFTs, it is apparent that in high light environments, such as LCTV projectors, the photocurrents in unshielded TFTs can be two to three orders of magnitude greater than the dark currents. From the channel length and gate and drain bias dependences, the photocurrent was identified as arising from both optical generation in the drain space charge region and diffusion from the bulk channel. The weak dependence of the photocurrent on drain bias meant that field relieving structures, used for the reduction of dark currents, had a more limited effect upon photocurrents. Spectral photocurrent measurements yielded a value for the recombination lifetime, in a columnar poly-Si TFT, of approximately 2*10-10 s. The detailed spectral response was shown to be due to interference effects in the multiple layer thin film structure. - Author(s): A. Pecora ; G. Tallarida ; G. Fortunato ; L. Mariucci ; . Reita ; P. Migliorato
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 33 –37
- DOI: 10.1049/ip-cds:19949829
- Type: Article
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The application of bias stress with high source-drain voltage and different gate voltages in polycrystalline silicon thin-film transistors produces marked modifications both in the off current as well as device transconductance. These effects are explained in terms of hot-carrier effects related to a combination of charge injection into the gate insulator and formation of interface states near the drain. - Author(s): J.R. Ayres and N.D. Young
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 38 –44
- DOI: 10.1049/ip-cds:19949951
- Type: Article
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Hot carrier induced degradation effects have been characterised in both discrete poly-Si TFTs and poly-Si circuits. DLTS measurements on individual TFTs have been used to confirm an increase in fast trapping state density which was consistent with the DC current/voltage characteristics of the TFTs. The increase in fast trapping state density occurred in the drain half of the device and was continuous in energy across the band gap between at least 0.1 and 0.5 eV below the conduction band. The effects observed were qualitatively similar in both as-deposited columnar poly-Si TFTs and poly-Si TFTs fabricated from furnace crystallised films deposited in an initially amorphous state. Digital NMOS poly-Si circuits running under accelerated drive conditions undergo degradation caused by hot carrier effects in the TFTs which support the high drain biases. However, a stable dynamic shift register suitable for LC-TV row drive applications has been demonstrated. This was achieved by using the fact that devices with a longer total channel length are more stable with respect to hot carrier induced degradation than short channel length devices. - Author(s): M. Quinn ; P. Migliorato ; C. Reita ; A. Pecora ; . Tallarida ; G. Fortunato
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 45 –49
- DOI: 10.1049/ip-cds:19949948
- Type: Article
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Since the performance of both analogue and digital circuits is heavily dependent on device output resistances, accurate simulation of these circuits requires that the saturation regime of the device output characteristics be carefully modelled. However, deviations from the gradual channel approximation, even at drain voltages below saturation, are observed in polysilicon thin-film transistors (TFTs). This paper investigates the effects of nonohmic conduction mechanisms on the output characteristics, and accounts for the excess current through a simple physical model suitable for implementation in a circuit simulator. The model is then used to investigate high-field effects in polysilicon TFTs. - Author(s): M.J. Edwards
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 50 –55
- DOI: 10.1049/ip-cds:19949828
- Type: Article
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A number of circuits that form the basic elements needed for integration of the drive circuits for active matrix LC displays have been investigated. The circuits have been fabricated using a low temperature polysilicon process and measurements have been made of the circuit performance. NMOS and CMOS circuits have been compared and while ratioed NMOS circuits have a poor performance in terms of speed and power, ratioless NMOS and CMOS circuit can both provide high-speed low-power operation. - Author(s): S.M. Fluxman
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 56 –59
- DOI: 10.1049/ip-cds:19949947
- Type: Article
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Digital circuits for a fully integrated active matrix liquid-crystal display (LCD) have been designed and fabricated with a low-temperature polysilicon thin-film-transistor process. Measurements of the CMOS inverters, static and dynamic shift registers, line memory latches and output drivers for the display are presented. A comparison is made of the results of measurement and simulation of the circuits using a thin-film-transistor-circuit model developed for the SPICE program. The model was used for the display circuit optimisation. The fully integrated active matrix LCD is also described. - Author(s): C. Reita and S. Fluxman
- Source: IEE Proceedings - Circuits, Devices and Systems, Volume 141, Issue 1, p. 60 –64
- DOI: 10.1049/ip-cds:19949950
- Type: Article
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The paper illustrates the use of poly-Si thin film transistors (TFTs) to fabricate analogue circuits and in particular operational amplifiers (opamps). A brief description of the peculiarities of poly-Si technology and their effects on the design of analogue circuits is given and some results obtained with low-temperature processes on two designs are discussed.
Current status and future prospects of poly-Si devices
Low-temperature (≤600 degrees C) polysilicon thin-film transistors
Optoelectronic and structural properties of polysilicon produced by excimer laser and furnace crystallisation of hydrogenated amorphous silicon (a-Si:H)
In-situ phosphorous-doped VLPCVD polysilicon layers for polysilicon thin-film transistors
Large-area shower implanter for thin-film transistors
Photocurrents in poly-Si TFTs
Hot-hole-induced degradation in polycrystalline silicon thin-film transistors: experimental and theoretical analysis
Hot carrier effects in devices and circuits formed from poly-Si
High-field effects in polysilicon thin-film transistors
NMOS and CMOS polysilicon drive circuits for liquid crystal displays
Design and performance of digital polysilicon thin-film-transistor circuits on glass
Design and operation of poly-Si analogue circuits
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