Online ISSN
1755-4543
Print ISSN
1755-4535
IET Power Electronics
Volume 4, Issue 8, September 2011
Volumes & issues:
Volume 4, Issue 8
September 2011
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- Author(s): Y. Zhao ; W. Li ; Y. Deng ; X. He
- Source: IET Power Electronics, Volume 4, Issue 8, p. 851 –859
- DOI: 10.1049/iet-pel.2010.0232
- Type: Article
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p.
851
–859
(9)
Non-isolated high step-up DC–DC converters are required widely in the industrial applications. Many of these conventional DC–DC converters have the disadvantages of operating at high duty-cycle, high switch voltage stress and high diode peak current. The proposed converter can provide very high voltage gain without operating at high duty-cycle by employing a coupled inductor, a switched capacitor and an additional diode. At the same time, the switch voltage stress is reduced greatly, which is helpful to reduce the conduction losses by using a low on-resistance switch. The presented converter employs a passive lossless clamp circuit instead of an active clamp circuit to recycle the leakage energy, which is simpler and easier to design. Zero-current switching turn on performance is achieved due to the leakage inductance, and the switch voltage is clamped to the voltage on the clamp capacitor, which is helpful to reduce the switch voltage stress. Moreover, the reverse-recovery energy of the output diode and the leakage inductance energy are recycled. Finally, a 500 W prototype has been built to verify the analysis. The maximum efficiency of the prototype is 96.9% and the efficiency is higher than 96% over a wide load range. - Author(s): H. Takaya ; K. Miyagi ; K. Hamada
- Source: IET Power Electronics, Volume 4, Issue 8, p. 860 –866
- DOI: 10.1049/iet-pel.2010.0102
- Type: Article
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p.
860
–866
(7)
A metal–oxide–semiconductor field-effect transistor (MOSFET) structure called FITMOS (floating island and thick bottom oxide trench gate MOSFET) has been successfully developed that exhibits outstanding low loss. This unique feature of the FITMOS is realised by fabricating deep trenches in the n-type drift layer, by forming p-type floating islands below the individual trenches using self-aligned ion implantation, and by fabricating trench gates with a thick oxide layer on the bottom. Then, the trade-off between the drain-to-source breakdown voltage and on-resistance has been further optimised by changing the shape of the floating islands from spherical to ellipsoidal. By improving the device structure, a breakdown voltage of 91 V and specific on-resistance of 41.5 mΩ mm2 have been obtained in a 4.5×4.5 mm square device with ellipsoidal floating islands. The relationship between the device structure and the reverse recovery characteristics is also investigated. - Author(s): R. Ansari ; M.R. Feyzi ; K. Akbari Hamed ; N. Sadati ; Y. Yasaei ; S. Ouni
- Source: IET Power Electronics, Volume 4, Issue 8, p. 867 –883
- DOI: 10.1049/iet-pel.2010.0158
- Type: Article
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p.
867
–883
(17)
This study presents an analytical approach for proper selection of output functions to be regulated for the Vienna rectifier such that the resultant closed-loop systems are minimum phase. Specifically, two different adaptive control methodologies based on the input–output linearisation are developed and categorised. In the first category, three output functions are introduced and imposed to be zero by using three dynamic feedback laws. On the basis of states to be regulated, four different cases are studied and it is shown that only one of these cases results in a one-dimensional zero dynamics with an asymptotically stable equilibrium point. In the second category, two output functions are defined and output zeroing problem is solved with two control inputs. In addition, the remaining control is used to feedback linearise the resultant two-dimensional zero dynamics. Eighteen different cases are studied to demonstrate that only in one of these cases, the corresponding zero dynamics is feedback linearisable. Stability properties of the adaptive systems are investigated to show that the proposed adaptive controllers are capable of DC output voltage regulation and power factor correction in the presence of parametric and non-parametric uncertainties. Finally, simulation results are presented to confirm the validity of the developed approaches. - Author(s): J. Kiilunen and L. Frisk
- Source: IET Power Electronics, Volume 4, Issue 8, p. 884 –890
- DOI: 10.1049/iet-pel.2010.0239
- Type: Article
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p.
884
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(7)
Because the time available for product design is usually much shorter than the projected operating life of the product, accelerated stress testing is commonly used to study the reliability of components, devices or larger systems. Under normal use conditions, products can be subjected to multiple simultaneous stressors. Consequently, it is also useful to use concurrent stresses during reliability testing. However, the combinatory effects of multiple stressors can be quite complex, which complicates failure analysis after testing. The usage of concurrent environmental stresses as a system-level reliability testing method is studied with the help of a frequency converter. The effects of different stresses on the failure modes and on the overall testing time were examined separately and simultaneously. The results show that with concurrent stresses the same kind of failure modes may be observed during testing as in normal service conditions and, more importantly, a significant reduction in testing time could be achieved when compared to that of single stress tests. - Author(s): K.M. Tsang and W.L. Chan
- Source: IET Power Electronics, Volume 4, Issue 8, p. 891 –898
- DOI: 10.1049/iet-pel.2010.0334
- Type: Article
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p.
891
–898
(8)
A novel controller based on the decoupling of single-ended primary inductor converter (SEPIC) state-space averaging model to four simple first-order systems is proposed. Instead of designing a single controller for a fourth-order SEPIC converter, four PI controllers are designed for the four decoupled systems. Combining the four PI controllers with the four decoupled systems forms a multi-loop feedback control system which is able to work at a wider operating condition. Circuit implementation of the proposed controller is presented and experimental results are included to demonstrate the effectiveness of the proposed design scheme. - Author(s): A.I. Maswood and F. Liu
- Source: IET Power Electronics, Volume 4, Issue 8, p. 899 –907
- DOI: 10.1049/iet-pel.2010.0139
- Type: Article
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p.
899
–907
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A recently introduced method of improving converter input current waveforms as well as power factor are re-evaluated under non-ideal operating conditions, that is, variable DC bus and unbalanced supply. The proposed method makes use of a novel controlled front-end diode rectifier of a rectifier–inverter structure. The technique involves the use of bi-directional bi-pass switches across the front-end rectifier, with a dSPACE-based intelligent control algorithm. The operation of the converter is fully analysed as possible DC/AC drives and a complete design example is provided. The main feature of the topology is low cost, small size, high power factor and simplicity. It is found to be a universal retrofit for DC drives, and in the front-end rectifier of existing three-phase AC drives, UPS etc. for power factor correction without any passive or active filtering. - Author(s): A. Çoban and I. Çadirci
- Source: IET Power Electronics, Volume 4, Issue 8, p. 908 –918
- DOI: 10.1049/iet-pel.2010.0175
- Type: Article
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p.
908
–918
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The analysis, design and implementation of an active-clamped and zero voltage switching and two-switch forward converter (AC-TSFC) equipped with a soft switched synchronous rectifier are presented. AC-TSFC is proposed for maximising the power conversion efficiency of two-switch forward converters (TSFCs), used in relatively high input voltage, low output voltage and high output current dc–dc converter applications. Operation principles and design requirements of AC-TSFC are given in detail. A 100 W, 200 kHz AC-TSFC with an input voltage range of 160–400 V dc and an output voltage of 5 V dc is designed, and a prototype is built. The converter performance is compared with that of alternative TSFC schemes, in view of their overall power conversion efficiency. Experimental results obtained on the implemented converter are in a good agreement with the theoretical ones, and verify the satisfactory performance of the proposed AC-TSFC. - Author(s): B.R. Lin and S.F. Wu
- Source: IET Power Electronics, Volume 4, Issue 8, p. 919 –926
- DOI: 10.1049/iet-pel.2010.0333
- Type: Article
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919
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This study presents a series resonant converter with series–parallel transformers in order to achieve zero voltage switching (ZVS) turn-on of MOSFETs, zero current switching (ZCS) turn-off of rectifier diodes, less voltage stress of rectifier diodes, less secondary winding with a full-wave rectifier and load current sharing. Two series resonant modules with the same switches are operated with the phase-shifted half switching cycle. In each resonant converter, primary windings of two transformers are connected in parallel in order to share the input current and reduce the root-mean-square (rms) current on primary windings such that copper losses of the transformers are reduced. The secondary windings of two transformers are connected in series in order to ensure that the primary currents are balanced to share load current. Thus the sizes of the transformer core and bobbin are reduced. Two full-wave diode rectifiers are adopted on output side such that the voltage stress of rectifier diodes is clamped to output voltage, rather than being two times the output voltage as in a conventional centre-tapped rectifier topology. Laboratory experiments with a 1000 W prototype were provided to describe the effectiveness of the proposed converter. - Author(s): L. Benadero ; V. Moreno-Font ; R. Giral ; A. El Aroudi
- Source: IET Power Electronics, Volume 4, Issue 8, p. 927 –935
- DOI: 10.1049/iet-pel.2010.0255
- Type: Article
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p.
927
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In this paper, continuous conduction mode (CCM) operation of a class of single inductor multiple output dc-dc converters is proposed. The power stage combines boost and buck-boost structures loading non-inverted and inverted outputs. The control strategy is based on current mode control under an interleaving scheme, in which each output is controlled by a specific channel. These channels use different dynamic references, which are obtained from a set of proportional-integral (PI) controllers associated to the voltage outputs. The dynamical behaviour of this system is described by means of a large signal averaged model and direct simulations of the switched circuit-based model. Small signal stability analysis of the slow scale dynamics is also carried out by using the averaged model. Finally, some experimental results are provided to validate the theoretical predictions and the numerical simulations. - Author(s): R.K. Behera and S.P. Das
- Source: IET Power Electronics, Volume 4, Issue 8, p. 936 –942
- DOI: 10.1049/iet-pel.2010.0149
- Type: Article
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p.
936
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In this study, a relay with hysteresis-based control technique is analysed for a three-phase three-level neutral point clamped (NPC) ac–dc converter. The converter draws sinusoidal current with unity power factor from the supply grid and keeps total dc-link voltage constant. The hysteresis-based current control has good dynamic response but suffers from variable switching frequency. The switching frequency characterisation of hysteresis current control based on time domain approach is more complicated for the multilevel converters. Therefore there is a need to address the characterisation based on frequency domain approach. Here, describing function method and Tsypkin's method are proposed for the switching frequency characterisation of the relay with hysteresis-based system. The proposed methods determine the maximum switching frequency and amplitude of the current tracking error and permit the calculation of maximum switching frequency in simple algebraic equations. The closed-loop control scheme of the relay with hysteresis-based current control is implemented for a three-phase three-level NPC ac–dc converter system. The performance of the proposed frequency domain characterisation has been studied using MATLAB/Simulink, and a laboratory model is developed for experimental verification. - Author(s): A. Alimardani ; B. Mazaheri ; B. Abdi ; S.H. Hosseinian
- Source: IET Power Electronics, Volume 4, Issue 8, p. 943 –950
- DOI: 10.1049/iet-pel.2010.0271
- Type: Article
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p.
943
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Harmonic pollution minimisation in voltage-source programmed pulse-width modulation (PPWM) inverters is defined as a time-limited optimisation problem in real-time applications with variable DC sources. In order to obtain minimum total harmonic distortion (THD) as the objective function, shuffled-frog-leaping algorithm (SFLA) is modified and employed to calculate the switching angles and compared with non-linear programming as a traditional optimisation method. In addition, particle swarm optimisation and three of its modified versions as popular evolutionary optimisation algorithms are employed to ensure the capability of the proposed optimisation method. Moreover, modified sinusoidal PWM (MSPWM) THD is compared with PPWM THD. Furthermore, as the DC bus voltage in some applications might have high variations (in amplitude or frequency of fluctuations) in a short time, to acquire adequate response speed to this variation of DC source of inverters in real-time control applications, a neural network (NN) is trained by the off-line calculated results of MSFLA for various desired modulation indexes (various DC voltages). Simulation results demonstrate the accurate and high-speed response of the designed NN. The main contribution of this study is to provide a fast accurate method which can track the variation of DC source of inverters with high-quality solutions in real-time control applications. - Author(s): P. Palanivel and S.S. Dash
- Source: IET Power Electronics, Volume 4, Issue 8, p. 951 –958
- DOI: 10.1049/iet-pel.2010.0332
- Type: Article
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p.
951
–958
(8)
Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the total harmonic distortion and enhances the output voltages from five level inverter. Three methodologies adopting the constant switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto typing, simple hardware and software design. The simulation and experimental results are presented.
High step-up boost converter with passive lossless clamp circuit for non-isolated high step-up applications
Improvement of floating island and thick bottom oxide trench gate metal–oxide–semiconductor field-effect transistor
Input–output linearisation of a fourth-order input-affine system describing the evolution of a three-phase/switch/level (Vienna) rectifier
System-level reliability testing a frequency converter with simultaneous stresses
Multi-loop controller for wide operating range single-ended primary inductor DC/DC converter
Unity power factor rectifier–inverter structure operating under unbalanced supply and variable DC bus voltage
Active clamped two-switch forward converter with a soft switched synchronous rectifier
Implementation of a series resonant converter with series–parallel transformers
Topologies and control of a class of single inductor multiple-output converters operating in continuous conduction mode
Analysis and experimental investigation for switching frequency characterisation of a three-level ac–dc converter using frequency domain approach
Modified shuffled-frog-leaping algorithm in company with neural networks for harmonic distortion minimisation in real-time control applications of programmed pulse-width modulation inverters
Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques
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