Interleaved DC–DC converters are extensively employed in high-power applications to reduce input/output current ripple, elements current stress, and improve reliability. In order to eliminate the switching losses in interleaved converters, zero voltage transition (ZVT) technique can be used. This study presents a new compact ZVT cell appropriate for interleaved converters. This cell employs a low number of elements while imposing no extra voltage and current stresses on the converter main semiconductors. The proposed cell is applied to an interleaved boost converter to achieve full soft switching feature. The resulting ZVT interleaved boost converter is completely analysed and its design procedure is provided. Also, the converter is compared with the latest prominent counterparts presented in literature. Besides, its operation and theoretical analysis are validated by a 200 W and 100 kHz prototype. Finally, the proposed ZVT cell is applied to other types of interleaved converters and a family of ZVT interleaved converters is introduced.

Grid-tied inverters, used in renewable energy sources, are exposed to distortions emitted by various sources including the reference signal, external power grid, and DC-link along with harmonics created by the pulse width modulation unit. However, the effect of these sources on grid-tied inverter output, especially near the resonant frequency of the inverter's filter, is unknown. In this study, a comprehensive harmonic model of the grid-tied inverter is presented by considering all three types of external sources. The proposed model can be utilised for low and high-frequency harmonic emission of grid-connected inverters. A new analytical expression is introduced as an indicator of the maximum possible individual grid current harmonic in the case of harmonic injection of multiple external sources. The impact of series damping resistor on harmonic rejection ability of the inverter is analysed at the range of frequencies around resonance. The simulation and experimental results fulfil the proposed harmonic model of the inverter.

The Internet of Things (IoT) connects billions of smart devices through wireless sensor networks (WSNs). However, to ensure the power supply for numerous passive devices in a WSN, it is necessary to replace batteries periodically, which will undoubtedly increase maintenance costs. This study proposes a capacitive coupling structure that is different from the previous capacitive power transfer (CPT) structures. The proposed structure can allow the positional variation of the receiver, and multiple receivers to be charged at the same time. Both theoretical and experimental results demonstrate that the power transmission is less affected by the positional variation of the pickup plates in the vertical and horizontal directions. In this study, all coupling capacitors between the plates are considered and the equivalent circuit model is derived. Further output characteristics of the circuit are derived and analysed. The dimensions of the structure are designed and simulated by using the EM full wave simulation. A prototype is designed to verify that a battery can be charged based on capacitive coupling. A 60 mAh rechargeable lithium-ion button battery is fully charged in 250 min, and the output power is ∼36 mW during charging.

In the LCL-filtered grid-tied inverter, the classical low-cost control strategy which is composed of the single converter-side current control and the unit grid voltage feedforward compensation, is commonly employed to inject the sinusoidal current into the utility. However, the inverter output admittance features the non-passive behaviour, which indicates that the harmonic currents may be amplified under the disturbances of the grid voltage and the grid impedance. Therefore, two dedicated current loops based on only the converter-side current feedback are proposed, which consist of the low-pass filter-based current regulation and the high-pass filter-based active damping (HFAD). The mixed asymmetrical regular sampling method is further used to reduce the control delay of the HFAD. Moreover, the low-pass filter-based feedforward is developed to make a compromise between the disturbance rejection and the stability. Fair comparisons with other typical control strategies are made through analysing the virtual resistor in parallel with the filter capacitor, which reveals that the positive virtual resistance at the frequency lower than half of the switching frequency is maintained. With the elaborated control parameters, the exhaustive experimental results finally verify the effectiveness of the proposed method in passivating the inverter output admittance.

Valley switching is one of the most efficient methods to decrease the switching losses in DC/DC converters. It uses a resonance between the converter's inductor and parasitic output capacitance of a metal–oxide–semiconductor field-effect transistor. In this study, the drawbacks of the valley switching in buck light-emitting-diode (LED) drivers are investigated. It shows that in spite of decreasing the switching losses, the valley switching method reduces its efficiency in some conditions. Also, it is clarified that the valley switching method not only causes current fluctuation in boost power factor correction converters but also malfunctions the buck LED drivers' performance. In this study, a semi-valley switching and its implementation are introduced to solve these problems. In general, it is shown that the proposed method improves both the efficiency and the performance of the buck LED driver, simultaneously. The methodologies are implemented in an experimental prototype to verify the proposed method.

In this study, a novel converter which integrates three capacitor clamped circuits and coupled inductor is proposed for high voltage gain. Compared with classical clamped circuit, these clamped circuits which are composed of one diode and three capacitors are used to improve voltage gain and achieve a continuous input current in this proposed converter. The proposed converter has four different clamped circuits, which can be divided into two types, including horizontal clamped and vertical ways. Moreover, each type of new clamped circuit corresponds to two different clamped circuits. This makes the designer have more selections to recycle the energy stored in leakage inductor. Besides, one of the three capacitors is connected in series with the output capacitor to efficiently reduce the voltage stress across the output capacitor, and voltages of both of them are less than half output voltage. Finally, in these converters, a converter based on three capacitor clamped circuit as a representative is analysed in detail. A prototype circuit is established in the laboratory to demonstrate the performances of this converter.

This study deals with (efficiency-power density) pareto optimisation of medium frequency transformers (MFTs) with considerations of voltage and frequency (Vf) constraints of semiconductors for mega-watt range input-series output-parallel (ISOP) connected dual-active bridges (DABs). A simple design methodology to include the Litz wire configuration in the optimisation process is proposed. Based on the presented design methodology, the effects of the semiconductors blocking voltage and switching frequency on the -pareto optimisation are evaluated. First, an idealised optimisation is carried out to understand the general behaviour of the optimum point. Second, brute-force optimisation is utilised to find the practical optimum solution based on the market availability of MFT components. Designing MFTs for a 1 MW 10 kV/600 V ISOP-DAB converter is the subject of numerical studies. The best trade-off between is selected as the final optimal solution and its design correctness is validated using three-dimensional finite-element analysis. Experimental tests on a 3 kW downscaled MFT prototype show that the proposed method is valid in practice.

A novel semi-isolated high step-up double-input converter with current-fed inputs is introduced in this study. The proposed converter can operate in double-input mode and single-input mode. It can manage the collected power from both inputs effectively. In addition, it makes a gentle transition between the modes, without the need for an abrupt change in pulse pattern, and does not utilise a breaker switch. Meanwhile, the converter preserves soft-switching as well as a few number of semiconductors (three switches and three diodes). These items have improved the efficiency of the converter to 94.5%. Moreover, it is a high-voltage gain (more than 13). Also, both input ports are current-fed, so the input currents are smoothed. These features make the converter compatible with hybrid renewable energy applications. Furthermore, all components are engaged in both modes, which results in an improved component's utilisation factor. A thorough analysis has been conducted to prove the characteristics mentioned above of the proposed converter. Theoretical analysis has been verified by simulation and experimental results of a 200 W prototype.

This study deals with steady-state analysis and control of a step-up interleaved winding cross-coupled inductor DC–DC converter with high voltage gain and reduced voltage stress across semiconductors using voltage multiplier cells (VMCs). Because of the interleaved scheme, the thermal stress is reduced and the input current ripple is minimised. The leakage energy is recycled by passive lossless clamp circuit to the output. Meanwhile, the voltage stress across the semiconductors is substantially low. Hence, MOSFETs with less ON-state resistances and diodes with a less forward voltage drop can be utilised that improves the circuit performance. The operation principle and the steady state are discussed. Small-signal modelling of the proposed converter is derived via state-space averaging technique and a dual loop controller for output voltage regulation is designed. The adopted strategy utilises a fast dynamical inner loop to control the input current and an outer loop for the output voltage regulation. Finally, a 1 kW prototype with 60 V–1 kV voltage conversion is fabricated and tested to probe the carried analysis.

Hybrid energy storage system (HESS) consists of different electrical storage devices with complementary characteristics to satisfy both the energy and power requirements of the load. This study presents an improved frequency sharing algorithm for battery/ultracapacitor (UC) HESS in the presence of delay. Time delay is inevitable with the digital implementation of control algorithms. Presence of delay deteriorates the transient response of the system by limiting the bandwidth of inner current loops. The DC-link voltage will settle only after settling of the slower loop, i.e. battery loop, hence the presence of delay will make the system response slower in conventional methods. However, the improved algorithm shares battery current loop error during transients with faster UC current loop and hence DC-link voltage settling becomes faster. Furthermore, for safe and efficient operation, an energy management algorithm (EMA) has been designed that ensures nominal UC voltage and other operational constraints as described in the study. To analyse the effect of UC voltage control loop on the operation of the DC-link voltage control loop during transients, UC voltage control loop with different bandwidths have been designed and tested. Microcontroller based implementation was done for experimental verification of the improved control algorithm and EMA.

This study proposes an extension to the well-known Fryze power theory, which allows the development of a mathematical procedure that defines a global factor for the active and non-active power processing in pulse-width modulated (PWM) dc–dc converters. This global factor is the dc power factor. The proposed extension is a vector representation of periodic currents and voltages mapped into a k-dimensional Euclidean space, which permits that all non-active power of all converter elements to be collected into a single figure of merit. To validate the approaches, a 220 W prototype of an isolated dc–dc Ćuk converter architecture was implemented and evaluated. Experimental results have confirmed that both total non-active power, the proposed dc power factor, and system efficiency are correlated. In the worst case of step-down mode, the converter prototype presented the lowest total non-active power of ∼25 var for the turns ratio of 0.567, resulting in the highest dc power factor of 0.135 and prototype efficiency of 80.6%. In step-up mode, it was obtained the lowest total non-active power of ∼1.14 kvar for the turns ratio of 1.764, resulting in the highest efficiency of 88.3% and dc power factor of 0.145.

In this study, a new zero voltage switching (ZVS) synchronous buck converter with ultra-high step-down conversion ratio is introduced. By combining coupled inductors and energy-transferring capacitors, operating duty cycle is significantly extended while the voltage stress across the switches is reduced. Thereby, extremely low voltage gain can be achieved and the conduction loss is reduced owing to using switches with lower voltage rating. Also, by applying the interleaved method and complementary pulses for switches, the current stress and the output current ripple are reduced. In the proposed converter, soft switching condition is achieved for all switches without any auxiliary circuit. As a result, the overall efficiency of the introduced converter is improved. The converter operation and its design considerations are discussed. Experimental results are presented to validate the theoretical analysis.

This study proposes a novel non-inverting buck–boost converter topology with extra-wide operational zones under both continuous current mode (CCM) and discontinuous current mode (DCM), by introducing a four-mode modulation (4MM) strategy. The proposed 4MM method is able to eliminate the operation dead zone, thus extending the operation zones of the buck–boost converter to contain boost mode, extended boost mode, extended buck mode, and buck mode. Rigorous analyses and design principles are presented in detail to demonstrate the four-mode function through CCM and DCM operational investigations and illustrations. Theoretical analyses and parameter design are verified by software simulation and hardware experimentation in this study, which validates the proposed 4MM method and the functionality of the proposed 4MM-based buck–boost converter. They clearly indicate the superiority of the proposed 4MM-based four-switch non-inverting buck–boost converter over its conventional counterparts, posing wide applicability in industrial practices.

As a classical control algorithm for grid-connected ac–dc converters, the conventional proportional–integral (PI) based direct power control (DPC) has several disadvantages, including the complexity of tuning PI parameters and poor dynamic performance. To tackle those drawbacks, this study presents a simple model predictive power control (MPPC) scheme with pulse-width modulation stage for single-phase ac–dc converters. Distinct from previous MPPC schemes, the proposed approach is formulated in terms of the terminal trajectory of modulated voltage vector, which is defined as an elliptic region. From the elliptical trajectory point of view, the proposed approach applies a cost function to predict an optimal radius of elliptic trajectory instead of the outputs of inner-loop PI controllers in PI-based DPC. To solve the parameter sensitiveness problem of MPPC schemes, a quantitative relationship between the predicted powers and their references considering inductance mismatch is analysed in detail. Then, an inductance estimation method is developed according to the analysis. A comprehensive experimental comparison with conventional PI-based DPC, and finite-control-set MPPC schemes have been conducted to verify the effectiveness of the proposed scheme.

It is important to reduce both the size and parasitic of power modules when designing a layout. However, the layout design often relies on experience and was time-consuming. The problem is particularly prominent in silicon carbide (SiC) modules, which requires more parallel dye compared with silicon counterparts. In this study, an algorithm for multi-chip SiC module layout design automation is proposed, which combines genetic algorithm, candidate searching idea, parallel operation and simplified evaluation models for enhancing computational efficiency with reasonable accuracy. A 12-chip half bridge SiC module is studied to verify the feasibility of the proposed method. The results indicate the method is robust and efficient, and can generate optimal layouts with low parasitic inductance and resistance as well as small footprint. It is believed that the method is feasible to guide the automatic optimal layout design for multi-chip SiC modules, targeting small footprint and low parasitic.

Recently, model predictive control has been widely used to control grid-connected inverters due to its advantages. However, the conventional model predictive control methods usually require two AC voltage and current sensors to sample the grid voltages and currents. Particularly, the DC voltage sensor is also required to calculate the values of the voltage vectors. The inverter will lose its stability once these sensors fail. Thus, in this study, to improve the operational reliability of the grid-connected inverters, a sliding mode observer-based AC voltage sensorless model predictive control is proposed. First, a sliding mode observer is designed to estimate the grid voltage. Next, a new adaptive compensation strategy is proposed to remove the phase and amplitude errors caused by the low-pass filter. The main novelty of this compensation strategy is that it is immune to the actual grid frequency. Therefore, the grid voltage can be identified accurately, even under frequency deviation conditions. Besides, the stability and parameter designing method of the sliding mode observer is also analysed to provide a theoretical basis for its implementation. Finally, based on the observed grid voltage, the AC voltage sensorless model predictive control is achieved. Detailed comparative experimental results show the validity of the proposed method.

This study presents a new boost DC-link integrated multilevel inverter (BDIMLI) topology for single-phase stand-alone photovoltaic applications. The BDIMLI is realised by the integration of two two-level boost DC-link converters (TBDCs) with a hybrid H-bridge inverter using symmetrical voltage sources. Conventional cascaded multilevel inverters require a large number of isolated DC source and circuit components. On the other side, switched capacitor multilevel inverter topologies require less number of sources and components, but need bulky capacitors. The proposed TBDC units charge the capacitors to the desired voltage with the high switching frequency, hence require less capacitance and component count. The proposed topology with proper selection of capacitor voltage levels can produce 9-, 11- and 13-level outputs without altering any circuit components. Besides, the proposed topology produces low-frequency common-mode voltage. The comprehensive analysis of BDIMLI in comparison with recent multilevel inverter topologies is presented. An experimental prototype of BDIMLI is built and its dynamic behaviour with different load conditions is presented for both 9- and 13-level operations.

Laser-based wireless power transmission (LWPT) systems are one of the most promising systems in the long-range wireless power transfer field. However, few studies have focused on the efficiency characteristics of LWPT systems. Therefore, most LWPT systems are open-loop systems, making it difficult to best utilise their lasers and photovoltaic cells, thus preventing the system efficiency from being further improved. In this study, a closed-loop power control method is proposed for LWPT systems to explore the best performance conditions for such systems. To this end, the efficiency characteristics of a system are investigated by means of theoretical analysis and experimental measurements. The results show that the duty cycle of the laser input current is one of the key factors for improving the system efficiency. Then, a dual closed-loop controller, which includes an optimal duty cycle search algorithm, is proposed based on the obtained system characteristics. Finally, a small-scale prototype is fabricated and tested in the laboratory to verify the effectiveness of the proposed power control method.

In this study, a three-port DC–DC converter is proposed based on quadratic boost converter. The proposed converter contains paths to enable the flow of power from input source to load and battery. Furthermore, it makes a path available to energise the load by the battery. The proposed converter has a bidirectional path using two additional switches and two diodes. Power flows from the input source and the battery to the load in a single-stage resulting in higher efficiency. The proposed converter has three switches and two duty cycles defined. By adjusting the duty cycles, maximum input power and output voltage can be regulated based on the input source power and the battery condition. To control the proposed converter, three operation modes are defined. In order to design the control system, the proposed converter is analysed and the small-signal models are obtained. Using a decoupling network for the integrated small-signal models, separated closed-loop controllers are designed. Finally, a prototype for the proposed converter is prepared to validate feasibility and effectiveness of the proposed converter and the control method by experimental results.

This study reports a newly designed induction heating system for efficient, fast, and safe flow-through heating. The system has a very simple architecture, which is composed of a transmitting coil, an isolating plastic pipe, and an embedded metal shell. Wireless energy transfer from the external coil to the internal metal shell through the pipe is essential for decreasing losses. Also, a large contact surface between a fluid and the immersed shell enables rapid heat transfer. The proposed heating system was systematically investigated for different shell geometries and the results were compared with a commercially available conductive flow-through heating device. As a proof-of-concept demonstration, a prototype of the designed induction heating system was manufactured and the heating measurements were conducted with water. Power transfer efficiency of the prototyped induction heating system was measured to be 97%. The comparative study indicates that such high-efficiency induction flow-through heating system offers a great potential for replacing the conventional conductive heating device used in household applications in which the rapid and compact heating is desired.

Normal phase-shift and modified pulse-width modulation gating schemes are proposed for a full bridge high-frequency capacitor–inductor–inductor (CLL) resonant DC–DC converter, and its performance is analysed in this study. Detailed modelling and the steady-state analysis of the converter are performed by using the fundamental harmonic approximation approach. Various modes of the converter operation with both the gating schemes are described and examined in detail. Zero-voltage switching of all the main switches is achieved by designing the resonant converter to operate in the above resonance mode. The optimum design of the converter is illustrated with the help of a flowchart and design curves. PSIM simulation is carried out and the experimental prototype is built to substantiate theoretical performance predictions. The simulation and experimental results are presented and compared.

A 10 MHz synchronous boost converter with the subthreshold startup scheme and predictive dead-time control for energy-harvesting systems is presented in this study. The input feed-forward technique is adopted to achieve a fast line response, and a three-stage startup technique is proposed to realise subthreshold voltage startup without using any extra startup circuits or special devices. Moreover, the efficiency of the high-frequency converter can be improved by the proposed predictive dead-time control with a high resolution of ∼300 ps. The proposed converter is implemented in a standard 0.18 μm complimentary metal oxide semiconductor process and occupies a die area of 1.4 × 1.5 mm². Experimental results show that the input voltage ranges from 0.3 to 1.5 V at 1.8 V output, and the minimum startup voltage is 0.3 V. Under V _IN = 1.5 V, V _OUT = 1.8 V and 150 mA load, the power efficiency can be improved by 2.6% because of the proposed predictive dead-time control. The peak efficiency can reach 90.7% under V _IN = 1.5 V. The line transient response can be improved with small overshoot voltage at the output.

Series and parallel resonance tend to occur and cause harmonic distortion when the distribution system contains a shunt power capacitor to compensate inductive load and dynamic capacitor (D-CAP) to suppress harmonics. This study focuses on the series and parallel resonance active damping of three-phase buck-type D-CAP, so as to achieve better power quality control. Two virtual resistor damping methods for series resonance, D-CAP power capacitor voltage or D-CAP front-end buffer inductor current feedback, are introduced and compared. Then, parallel resonance is damped by generating certain harmonic currents in the phase with the selective harmonic voltage at the point of common coupling (PCC), equivalent to controlling the D-CAP as a virtual harmonic resistor. In addition, the power balance of D-CAP is interpreted to ensure no additional energy control loop is needed for the active damping. To further improve the parallel resonance damping, the self-adjusted damping gain is proposed by the closed-loop regulation of harmonics in PCC voltage. Finally, coordinated control between reactive and multiple harmonic currents is introduced for the whole combined control to avoid over-modulation. A wide variety of experimental results from a 33 kVar/220 V laboratory prototype are provided to demonstrate the validity of the combined control.

Unity power factor rectifiers find applications in modern utility systems and consumer electronic devices. However, a dedicated rectifier is required for a given load. In this study, a Unity Power Factor (UFP) power block is described which can generate two DC outputs, one buck and one boost, with a reduced number of switches and associated driver circuits. The topology adapts well with conventional control as it retains the dynamic behaviour of a buck and boost topology. While supplying simultaneous loads it exhibits minimal cross-regulation interference between the outputs. The controller implementation for the proposed power block is described and its difference with the conventional Power Factor Correction (PFC) controller is outlined. The topology along with its control to regulate the outputs and force UPF operation are validated using a 200 W prototype with 110 V utility input and 180–24 V DC outputs.