In order to explore the mapping recognition of arc welding molten pool characterisation and penetration state, according to the idea of embedded system construction, this article adopts the idea of software and hardware co‐design to find the zero‐crossing point of the second derivative in welding image edge detection, and give a threshold. When the absolute value of the first‐order derivative exceeds the threshold and has a different sign with the first‐order derivative of the previous edge, it is judged as a valid edge. The welding current adopts a symmetrical pulsed AC square wave, and the proportion of heat flow input is high. At the base current, the arc light is darker, so a clear image is obtained. This article designs a simulation experiment to verify the effect of the embedded system in this article. From the experimental research, it can be known that the embedded system constructed in this article can play a certain role in the mapping recognition of the arc welding molten pool characterisation and penetration state.

(1) It conducts application demand analysis and function definition according to user requirements; (2) It carries out system software and hardware division and collaborative design according to performance index requirements; (3) The software part and the hardware part are designed and implemented separately, and the interface is integrated; (4) Based on the cooperative work of software and hardware, it performs system‐level verification, testing and optimisation.image

The intellectual properties (IP) protection of deep neural networks (DNN) models has raised many concerns in recent years. To date, most of the existing works use DNN watermarking to protect the IP of DNN models. However, the DNN watermarking methods can only passively verify the copyright of the model after the DNN model has been pirated, which cannot prevent piracy in the first place. In this paper, an active DNN IP protection technique against DNN piracy, called ActiveGuard, is proposed. ActiveGuard can provide active authorisation control, users' identities management, and ownership verification for DNN models. Specifically, for the first time, ActiveGuard exploits well‐crafted rare and specific adversarial examples with specific classes and confidences as users' fingerprints to distinguish authorised users from unauthorised ones. Authorised users can input their fingerprints to the DNN model for identity authentication and then obtain normal usage, while unauthorised users will obtain a very poor model performance. In addition, ActiveGuard enables the model owner to embed a watermark into the weights of the DNN model for ownership verification. Compared to the few existing active DNN IP protection works, ActiveGuard can support both users' identities identification and active authorisation control. Besides, ActiveGuard introduces lower overhead than these existing active protection works. Experimental results show that, for authorised users, the test accuracy of LeNet‐5 and Wide Residual Network (WRN) models are 99.15% and 91.46%, respectively, while for unauthorised users, the test accuracy of LeNet‐5 and WRN models are only 8.92% and 10%, respectively. Besides, each authorised user can pass the fingerprint authentication with a high success rate (up to 100%). For ownership verification, the embedded watermark can be successfully extracted, while the normal performance of DNN models will not be affected. Furthermore, it is demonstrated that ActiveGuard is robust against model fine‐tuning attack, pruning attack, and three types of fingerprint forgery attacks.

An active deep neural networks (DNN) intellectual property protection technique against DNN piracy, named ActiveGuard is proposed. ActiveGuard can provide active authorisation control, users' identities management, and ownership verification for DNN. Specifically, for the first time, ActiveGuard exploits well‐crafted rare and specific adversarial examples as users’ fingerprints to distinguish authorised users from unauthorised users. Authorised users can input their fingerprints to the DNN for identity authentication and then obtain normal usage, while unauthorised users will obtain a rather poor model performance.image

Transient execution attacks such as Spectre and Meltdown exploit speculative execution in modern microprocessors to leak information via cache side‐channels. Software solutions to defend against many transient execution attacks employ the lfence serialising instruction, which does not allow instructions that come after the lfence to execute out‐of‐order with respect to instructions that come before the lfence. However, errors and Trojans in the hardware implementation of lfence can be exploited to compromise the software mitigations that use lfence. The aforementioned security gap has not been identified and addressed previously. The authors provide a formal method solution that addresses the verification of lfence hardware implementation. The authors also show how hardware Trojans can be designed to circumvent lfence and demonstrate that their verification approach will flag such Trojans as well. The authors have demonstrated the efficacy of our approach using RSD, which is an open source RISC‐V based superscalar out‐of‐order processor.

Serialising instructions such as lfence are used to guard modern microprocessors against Spectre‐like transient execution attacks. However, bugs and Trojans can render the solution ineffective without impacting programme correctness. We provide a formal verification methodology which guarantees the integrity of the lfence instruction.image

In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features.

The authors present a novel self‐timing first‐edge take‐all circuit for on‐chip communication systems.image

Modern deep neural networks typically have some fully connected layers at the final classification stages. These stages have large memory requirements that can be expensive on resource‐constrained embedded devices and also consume significant energy just to read the parameters from external memory into the processing chip. The authors show that the weights in such layers can be modelled as permutations of a common sequence with minimal impact on recognition accuracy. This allows the storage requirements of FC layer(s) to be significantly reduced, which reflects in the reduction of total network parameters from 1.3× to 36× with a median of 4.45× on several benchmark networks. The authors compare the results with existing pruning, bitwidth reduction, and deep compression techniques and show the superior compression that can be achieved with this method. The authors also showed 7× reduction of parameters on VGG16 architecture with ImageNet dataset. The authors also showed that the proposed method can be used in the classification stage of the transfer learning networks.

Modern deep neural networks typically have some fully connected layers at the final classification stages. These stages have large memory requirements that can be expensive on resource‐constrained embedded devices and also consume significant energy just to read the parameters from external memory into the processing chip. The authors show that the weights in such layers can be modelled as permutations of a common sequence with minimal impact on recognition accuracy.image