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Online ISSN 1751-861X
Print ISSN 1751-8601

IET Computers & Digital Techniques

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  • VLSI implementation of anti-notch lattice structure for identification of exon regions in Eukaryotic genes
  • Lower complexity error location detection block of adjacent error correcting decoder for SRAMs
  • Accelerated LiDAR data processing algorithm for self-driving cars on the heterogeneous computing platform
  • Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology
  • Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g
  • Multi-core hardware realisation of the quasi maximum likelihood PPS estimator
  • Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source
  • Sensitivity analysis of testability parameters for secure IC design
  • LUT-based high-speed point multiplier for Goldilocks-Curve448
  • Amdahl's law in the context of heterogeneous many-core systems – a survey
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