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Online ISSN 1751-861X
Print ISSN 1751-8601

IET Computers & Digital Techniques

eFirst articles

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  • An Approach of Genetic Algorithm for Power Aware Testing of 3D IC
  • Power-efficient reliable register file for aggressive-environment applications
  • Yield modelling and analysis of bundled data and ring-oscillator based designs
  • DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems
  • Leveraging Design Diversity to Counteract Process Variation: Theory, Method, and FPGA Toolchain to Increase Yield and Resilience In-situ
  • Updating the sets of target faults during test generation for multiple fault models
  • Throughput/area optimised pipelined architecture for elliptic curve crypto processor
  • Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs
  • KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC
  • Soft-error reliable architecture for future microprocessors
  • Exploiting memory allocations in clusterised many-core architectures
  • Design of An extended 2D mesh network-on-chip and development of A fault-tolerant routing method
  • Mitigating information leakage during critical communication using S*FSM
  • Efficient hardware structure for extended Euclidean-based inversion over
  • Probabilistic timing analysis of time-randomised caches with fault detection mechanisms
  • Study of the monte–carlo fault injection simulator to measure a fault derating
  • Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs
  • RASSS: a hijack-resistant confidential information management scheme for distributed systems
  • HASTI: hardware-assisted functional testing of embedded processors in idle times
  • Removing constant-induced errors in stochastic circuits
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