The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead.

With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2-level and 3-level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called ‘SkipCache’, which allows an application to choose a 2-level or 3-level cache hierarchy during run-time. SkipCache dynamically tracks the applications at shared last-level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4-core chip multi-processor with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.

In integrated circuit (IC) burn-in, it is desirable to produce efficient input patterns to assist heating for circuit under test. This study proposes and demonstrates an approach which uses the genetic algorithm incorporating with a BACK-like procedure to generate the patterns which produce the maximal and/or uniform node transition as well as power dissipation for burn-in application. A multi-step strategy is applied in the algorithm, and a transition measure is defined to guide the backtracing of the BACK-like procedure, improving the efficiency in searching the target patterns. Experimental results show that the approach generates better pattern pairs which produce either the maximal transition count or the maximal power dissipation than that of all the other published results. It is also able to generate the pattern sequence which achieves more uniformly stressing, by 30% improvement statistically, for each gate of the circuit under test. The computation time, because of using a divide-and-conquer strategy in this approach, is also reasonable, making it useful in the practical IC burn-in application.

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward-traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo-based fault injection simulation on ISCAS'85 benchmark circuits.

The universal serial bus (USB) has some advantages like high transmission speed, plug-and-play and hot swapping, and has become the most popular interface standard for peripheral connections. However, such features also make it easier for a malicious user to extract confidential files from computer systems via USB ports. Consequently, to control the potential security risks of USB interface, many workplace and commercial corporations have directly forbidden their employees from using USB devices. To provide a flexible way of using USB without compromising security, this study proposes a novel secure control protocol for USB storage devices. The device and the server are required to complete mutual authentication and establish a session key used to encrypt the transferred files. The details of each phase of the new protocol are given. Security analysis demonstrates that the proposed protocol conquers those security pitfalls existing in the available protocols and can resist various attacks. Performance discussion indicates that the new protocol is also efficient enough for practical applications.

A new piecewise polynomial method is proposed to compute elementary functions by using high-order Taylor approximation. The high-order power terms of the series are proposed to be approximated by using simple and fast table lookup. Furthermore, the similarity and regularity among the Taylor coefficients can make possible the sharing of the lookup tables. The authors have developed an error analysis method to estimate the maximum error of the proposed approximation approach, and formulated the procedure for determining the hardware parameters in the approximation unit. Finally, the authors have designed a single-precision approximation unit for computing six common elementary functions. The coefficient sharing approach can result in at least 30.5% reduction in the coefficient lookup tables. Compared with a previous work by Piñeiro et al., the authors can save 27.91% of the lookup tables with some extra cost in computation hardware. Compared with the work by Alimohammad et al., 34.85% of the lookup tables can be saved with the same computation hardware cost. The authors conclude that the proposed approaches can effectively reduce the lookup tables required in the piecewise polynomial approximation for efficient elementary function computation.