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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 9, Issue 5, September 2015

Volume 9, Issue 5

September 2015

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    • Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor
      Reducing the system standby power of a personal computer
      H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture
      Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips
      Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality

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