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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 9, Issue 2, March 2015


Volume 9, Issue 2

March 2015

Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator
Truncated ternary multipliers
Use of input necessary assignments for test generation based on merging of test cubes
Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation

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