It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm². The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.

In this study, novel pipelined architectures, optimised in terms of throughput and throughput/area factors, for the SHA-512 cryptographic hash function, are proposed. To achieve this, algorithmic- and circuit-level optimisation techniques such as loop unrolling, re-timing, temporal pre-computation, resource re-ordering and pipeline are applied. All the techniques, except pipeline are applied in the function's transformation round. The pipeline was applied through the development of all the alternative pipelined architectures and implementation in several Xilinx FPGA families and they are evaluated in terms of frequency, area, throughput and throughput/area factors. Compared to the initial un-optimised implementation of SHA-512 function, the introduced five-stage pipelined architecture improves the both the throughput and throughput/area factors by 123 and 61.5%, respectively. Furthermore, the proposed five-stage pipelined architecture outperforms the existing ones both in throughput (3.4× up to 16.9×) and throughput/area (19.5% up to 6.9×) factors.

This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.

Multi-cycle tests, with two or more functional clock cycles between scan operations, can be used for test compaction. When tester limitations prevent primary input vectors from being changed at-speed, one of the possible solutions is to hold the primary input vector constant during the functional clock cycles of a multi-cycle test. However, this limits the level of test compaction that can be achieved. To provide an alternative to this solution, a new type of multi-cycle tests has been defined, where the primary input vector is changed during a clock cycle that is applied under a slow clock. This is followed by a run of the same vector applied under a fast clock. Transition faults are activated during the clock cycles that are applied under a fast clock. A test generation procedure that produces such test sets for transition faults has also been described. Experimental results demonstrate that the new type of tests can improve the ability to produce a compact test set for certain benchmark circuits.

Modern interconnect performance is greatly affected by crosstalk noise because of continuous decrease in wire separation and increase in its aspect ratio with technology scaling. Such noise is highly dependent on data transition patterns, coding techniques have been proposed to alleviate crosstalk delay by controlling these patterns. The complexity of available crosstalk avoidance codes, along with their associated overheads, increase rapidly with bus width. The lack of energy and area-efficient method to implement such codes has so far prevented their use in practical designs. This study presents a generic framework, which allows efficient implementations of crosstalk avoidance codes; the essence of the proposed approach is based on the partial coding concept. Quantitative analysis performed in 32 nm technology shows that substantial savings in area and energy costs can be obtained using the proposed technique compared with both existing coding solutions and conventional methods as shielding and repeater insertion.