Under an approach to test compaction called transparent scan, a scan circuit is considered as a sequential circuit where the scan-chain inputs and scan-select input are included in the set of inputs of the circuit. This provides the flexibility to interleave functional and scan clock cycles in arbitrary ways, and enhances the ability of transparent-scan sequences to detect target faults. These features are used in this study for reducing the input test data volume by using the same scan-chain input sequences with different scan-select sequences to define transparent-scan sequences. The circuits under consideration have a scan chain that includes their state variables, primary inputs and primary outputs. Scan-chain input sequences are computed based on a given conventional scan-based test set that includes compacted single-cycle and two-cycle test sets for single stuck-at and transition faults, respectively. The set of scan-select sequences is fixed. Using the same scan-chain input sequences for defining several transparent-scan sequences, with different scan-select sequences, allows more faults to be detected with the same set of scan-chain input sequences. This allows the number of scan-chain input sequences to be reduced compared with the number of tests in the conventional scan-based test set.

Numerous contributions on reverse conversion methods based on the Chinese Remainder Theorem (CRT), for residue number systems (RNS), have been regularly appearing in relevant literature. Reverse conversion is known as a slow RNS operation that becomes more complicated and slower for larger moduli sets. In this study, the authors examine four previous reverse converters for moduli set 𝓕 = {2 ^q − 1, 2 ^q + 3, 2 ^q + 1, 2 ^q − 3}. Three of these converters heavily utilise Read Only Memories (ROM), and the other one uses a Montgomery multiplier. In order to cut the costs and improve performance, the authors propose an adder-only two-stage New CRT conversion scheme that uses conjugate grouping of the moduli as {{2 ^q ± 1, 2 ^q ± 3}}. Also, manipulation of multiplicative inverse coefficients that are expressed as a series of power-of-two terms takes place via multi-operand addition instead of using ROMs and/or multipliers. This leads to roughly 22, 19 and 8% improvement in delay, area consumption and power dissipation, respectively, in comparison to the only previous ROM-less design for 𝓕. Moreover, use of no ROMs allows for pipelining, if desired. They also address four state-of-the-art converters and compare their performance with the authors (i.e. that of 𝓕), where none is faster than the proposed converter. They support their claims with analytical gate-level comparisons and via synthesis results.

This study presents an efficient method for converting a normalised binary number x (1 ≤ x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.

Cache miss can have a major impact on overall performance of many-core systems. A miss may result in extra traffic and delay because of coherency messages. This has been reduced in coarse-grain coherency protocols where only shared misses require a coherency message. Conventional off-chip methods manage the shared miss rate by relying on reuse histories. However the pertinent memory overhead that comes with reuse histories makes them impractical for on-chip multi-processor systems. In this study, a new scheme has been proposed to reduce shared cache miss rate in multi-processor system-on-chips that benefits from novel prefetching techniques to L2 caches from off-chip memories or other remote L2 caches located on-chip. In the proposed scheme, the previously proposed Virtual Tree Coherence (VTC) method has been extended to limit block forwarding messages to true sharers within each region. Instead of relying on exact reuse histories, shared regions are searched for regional, temporal and statistical similarities. These similarities are exploited for determining the sharers that should receive the forwarded blocks. The proposed method has been evaluated with Splash-2 workloads. Simulation results indicate that the proposed method has reduced shared miss count by up to 75%, and improved interconnect traffic by up to 47% compared with VTC.

Digital microfluidic (DMF) biochips offer a versatile platform for implementing several laboratory based biochemical protocols. These tiny chips can electrically control the dynamics of nanoliter volume of discrete fluid droplets on an electrode array by application of actuation patterns. One important step in biochemical sample preparation is dilution, where the objective is to prepare a fluid with a desired concentration factor. The protocols implemented on DMF biochips may require several different concentration values of a sample. In this study, the authors propose a scheme to produce such target droplets from a supply of an input sample and a buffer solution. Simulation results show a significant amount of savings in the number of mix-split steps and waste droplets in comparison to other methods for generating multiple concentration factors.