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Online ISSN 1751-861X Print ISSN 1751-8601

access icon free IET Computers & Digital Techniques

Volume 7, Issue 6, November 2013

Volume 7, Issue 6

November 2013

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    • Editorial
      A fault-tolerant core mapping technique in networks-on-chip
      HW/SW co-design of dedicated heterogeneous parallel systems: an extended design space exploration approach
      Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip
      Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip
      Temperature control in three-network on chips using task migration
      Unified multi-objective mapping and architecture customisation of networks-on-chip
      Hybrid wire-surface wave interconnects for next-generation networks-on-chip
      Prevention slot flow-control mechanism for low latency torus network-on-chip

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