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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 6, Issue 6, November 2012

Volume 6, Issue 6

November 2012

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    • Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique
      Behavioural synthesis utilising recursive definitions
      Comments on ‘Improving the speed of decimal division’
      Asymmetric large size multipliers with optimised FPGA resource utilisation
      Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation
      Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
      High-performance low-power sensing scheme for nanoscale SRAMs
      Image and video processing platform for field programmable gate arrays using a high-level synthesis

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