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image of Volume 6, Issue 5
Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 6, Issue 5, September 2012


Volume 6, Issue 5

September 2012

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    • Editorial: High-performance computing system architectures: design and performance
      Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
      Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n−1, 2n, 2n+1}
      Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture
      Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems
      Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links
      Application-specific topology generation algorithms for network-on-chip design
      Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor
      Throughput enhancement for repetitive internal cores in latency-insensitive systems

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